{{Short description|Computing technique}} {{refimprove|date=April 2012}} '''Write combining''' ('''WC''')<ref>{{cite web|url=http://download.intel.com/design/PentiumII/applnots/24442201.pdf|title=Write Combining Memory Implementation Guidelines|publisher=Intel|author=Intel|date=November 1998|accessdate=2010-11-02}}</ref> is a computer bus technique for allowing data to be combined and temporarily stored in a buffer{{snd}} the '''write combine buffer''' ('''WCB'''){{snd}} to be released together later in burst mode instead of writing (immediately) as single bits or small chunks.
==Technique== Write combining cannot be used for general memory access (data or code regions) due to the weak ordering. Write-combining does not guarantee that the combination of writes and reads is done in the expected order. For example, a <code>write</code>/<code>read</code>/<code>write</code> combination to a specific address would lead to the write combining order of <code>read</code>/<code>write</code>/<code>write</code> which can lead to obtaining wrong values with the first read (which potentially relies on the write before).
In order to avoid the problem of read/write order described above, the write buffer can be treated as a fully associative cache and added into the memory hierarchy of the device in which it is implemented.<ref>{{cite web|url=http://www.bearwindows.boot-land.net/af.htm|archive-url=https://web.archive.org/web/20080724002604/http://www.bearwindows.boot-land.net/af.htm|url-status=usurped|archive-date=July 24, 2008|title=Video Hardware Acceleration in DOS Environment|publisher=BearWindows Vault|author=BearWindows|date=2008-09-01|accessdate=2010-11-02}}</ref> Adding complexity slows down the memory hierarchy so this technique is often only used for memory which does not need strong ordering (always correct) like the frame buffers of video cards.
==See also== *Framebuffer (FB), and when linear: LFB *Memory type range registers (MTRR) – the older x86 cache control mechanism *Page attribute table (PAT) – x86 page table extension that allows fine-grained cache control, including write combining *Page table *Uncacheable speculative write combining (USWC) *Video Graphics Array (VGA), and Banked (BVGA) Frame Buffer
==References== {{Reflist}}
==External links== *[http://www.mdgx.com/umb.htm#FAS 6x86opt, ctppro, CTU, DirectNT, FastVid, fstorion, K6Speed, MTRRLFBE, S3 Speed Up & Write Allocate Monitor] enable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 and AMD K6 CPUs in Windows 9x, Windows NTx, DOS, OS/2 and Linux *[http://rayer.g6.cz/programm/programe.htm#MTRRLFBE MTRRLFBE] enable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 CPUs in Windows 9x and DOS *[https://web.archive.org/web/20030820203630/http://home.student.utwente.nl/r.muller/unirefresh/ctu/ CTU] (Internet Archive cached copy) enable LFB and Banked VGA Write Combining on AMD K6 CPUs in Windows 9x and DOS
Category:Computer buses Category:Computer memory