Page attribute table

{{Refimprove|date=October 2009}} The '''page attribute table''' ('''PAT''') is a [[processor supplementary capability]] extension to the [[page table]] format of certain [[x86]] and [[x86-64]] microprocessors. Like [[memory type range registers]] (MTRRs), they allow for fine-grained control over how areas of memory are [[CPU cache|cached]], and are a companion feature to the MTRRs.<ref>{{cite web | title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1 | url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf | publisher=Intel | date= | access-date=2017-05-30}}</ref>

Unlike MTRRs, which provide the ability to manipulate the behavior of caching for a limited number of fixed physical address ranges, Page Attribute Tables allow for such behavior to be specified on a [[Page (computer science)|per-page]] basis, greatly increasing the ability of the [[operating system]] to select the most efficient behavior for any given task.<ref>{{cite web | title=PAT (Page Attribute Table) in Linux kernel docs | url=https://www.kernel.org/doc/html/latest/x86/pat.html | date= | access-date=2020-06-02 | archive-date=2021-01-21 | archive-url=https://web.archive.org/web/20210121115331/https://www.kernel.org/doc/html/latest/x86/pat.html | url-status=dead }}</ref>

== Processors == The PAT is available on [[Pentium III]] and newer CPUs, and on non-Intel CPUs.

== See also == * [[Write-combining]]

== References == <references/>

== External links == * [http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1] see chapter 11, section 12.

[[Category:Virtual memory]] [[Category:X86 architecture]]