RDNA 3

{{Short description|GPU microarchitecture by AMD}} {{Use American English|date=April 2023}} {{Use mdy dates|date=April 2023}} {{Infobox GPU microarchitecture | name = RDNA 3 | image = AMD RDNA-3 Logo.png | caption = | alt =  | launched = {{Start date and age|2022|12|13}} | discontinued = | designfirm = AMD | manuf1 = TSMC | process = {{ubl |TSMC N4 (APUs)|TSMC N5 (GCD)|TSMC N6 (Navi 33 and MCD)}} | codename = {{ubl |Navi 31: Plum Bonito |Navi 32: Wheat Nas |Navi 33: Hotpink Bonefish}}

|products-desktop1 = Radeon RX 7000 series | products-hedt1 = Radeon Pro W7000 series | products-server1 =

| cuda-compute-version =  | directcompute-version =

| compute = {{ubl |Up to 122.8{{nbsp}}TFLOPS (FP16) |Up to 61.42{{nbsp}}TFLOPS (FP32) |Up to 1.919{{nbsp}}TFLOPS (FP64)}} | slowest = 1500 | slow-unit = MHz | fastest = 2500 | fast-unit = MHz | shader-clock = 2269{{nbsp}}MHz | l0-cache = 96{{nbsp}}KB (per {{abbr|WGP|Work Group Processor}}): {{bulleted list |32{{nbsp}}KB vector cache |16{{nbsp}}KB scalar cache}} | l1-cache = 256{{nbsp}}KB (per array) | l2-cache = up to 6{{nbsp}}MB | l3-cache = up to 96{{nbsp}}MB (16{{nbsp}}MB per MCD) | memory-support = GDDR6 | memory-clock = up to 20 Gbps | pcie-support = PCIe 4.0

| encode-codec = {{hlist |H.264 |H.265 |AV1}} | decode-codec = {{hlist |H.264 |H.265 |AV1}} | color-depth = {{hlist |8-bit |10-bit |12-bit}} | encoders = {{hlist |AMF |VCE}} | display-outputs = {{ubl |DisplayPort 2.1 |HDMI 2.1a |USB-C}}

| predecessor = RDNA 2 | variant = CDNA 3 (datacenter) | successor = RDNA 4 | support_status = Supported }} '''RDNA 3''' is a GPU microarchitecture designed by AMD, released with the Radeon RX 7000 series on December 13, 2022. Alongside powering the RX 7000 series, RDNA 3 is also featured in the SoCs designed by AMD for the Asus ROG Ally, Lenovo Legion Go, and the Steam Machine consoles.

== Background == On June 9, 2022, AMD held their Financial Analyst Day where they presented a client GPU roadmap which contained mention of RDNA 3 coming in 2022 and RDNA 4 coming in 2024.<ref>{{Cite web |last1=Smith |first1=Ryan |date=June 9, 2022 |title=AMD's 2022-2024 Client GPU Roadmap: RDNA 3 This Year, RDNA 4 Lands in 2024 |url=https://www.anandtech.com/show/17443/amds-client-gpu-roadmap-rdna-3-this-year-rdna-4-lands-in-2024 |archive-url=https://web.archive.org/web/20220609204322/https://www.anandtech.com/show/17443/amds-client-gpu-roadmap-rdna-3-this-year-rdna-4-lands-in-2024 |url-status=dead |archive-date=June 9, 2022 |website=AnandTech |language=en-US |access-date=April 8, 2023}}</ref> AMD announced to investors their intention to achieve a performance-per-watt uplift of over 50% with RDNA 3 and that the upcoming architecture would be built using chiplet packaging on a 5 nm process.<ref>{{Cite web |last1=Walton |first1=Jarred |date=2022-06-09 |title=AMD GPU Roadmap: RDNA 3 With 5nm GPU Chiplets Coming This Year |url=https://www.tomshardware.com/news/amd-rdna3-roadmap-chiplets-5nm |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref>

A sneak preview for RDNA 3 was included towards the end of AMD's Ryzen 7000 unveiling event on August 29, 2022. The preview included RDNA 3 running gameplay of ''Lies of P'', AMD CEO Lisa Su confirming that a chiplet design would be used, and a partial look at AMD's reference design for an RDNA 3 GPU.<ref>{{Cite web |last1=Wickens |first1=Katie |date=2022-08-31 |title=AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture |url=https://www.pcgamer.com/amds-lisa-su-confirms-chiplet-based-rdna-3-gpu-architecture/ |website=PC Gamer |language=en-US |access-date=2026-05-31|url-status=live}}</ref>

Full details for the RDNA 3 architecture were unveiled on November 3, 2022 at an event in Las Vegas.<ref>{{Cite web |date=2022-11-03 |title=AMD Unveils World’s Most Advanced Gaming Graphics Cards, Built on Groundbreaking AMD RDNA 3 Architecture with Chiplet Design |url=https://www.amd.com/en/press-releases/2022-11-03-amd-unveils-world-s-most-advanced-gaming-graphics-cards-built |url-status=dead |archive-url=https://web.archive.org/web/20221105004455/https://www.amd.com/en/press-releases/2022-11-03-amd-unveils-world-s-most-advanced-gaming-graphics-cards-built |archive-date=2022-11-05 |access-date=2026-05-31 |website=www.amd.com |language=en}}</ref>

== Architecture == === Chiplet packaging === For the first time ever in a consumer GPU, RDNA 3 utilizes modular chiplets rather than a single large monolithic die. AMD previously had great success with its use of chiplets in its Ryzen desktop and Epyc server processors.<ref>{{Cite web |last1=James |first1=Dave |date=2022-06-24 |title=AMD suggests a Ryzen-like design for RDNA 3 chiplets would be 'a reasonable inference' |url=https://www.pcgamer.com/amd-suggests-a-ryzen-like-chiplet-design-for-rdna-3-gpus-would-be-a-reasonable-inference/ |website=PC Gamer |language=en-US |access-date=2026-04-08|url-status=live}}</ref> The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President Sam Naffziger who had also lead the chiplet initiative with Ryzen and Epyc.<ref>{{Cite web |last1=Alcorn |first1=Paul |last2=Walton |first2=Jarred |date=2022-06-23 |title=Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger |url=https://www.tomshardware.com/features/gpu-chiplet-era-interview-amd-sam-naffziger |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref> The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort.<ref name="Brosdahl">{{Cite web |last1=Brosdahl |first1=Peter |date=2022-11-22 |title=AMD Lead Engineer Sam Naffziger Explains Advantages of RDNA3 Chiplet Design |url=https://www.thefpsreview.com/2022/11/22/amd-lead-engineer-sam-naffziger-explains-advantages-of-rdna3-chiplet-design/ |website=The FPS Review |language=en-US |access-date=2026-05-31|url-status=live}}</ref> The benefit of using chiplets is that dies can be fabricated on different process nodes depending on their functions and intended purpose. According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer.<ref name="Brosdahl"/> Alternatively, a large monolithic RDNA 3 die built on N5 would be more expensive to produce with lower yields.

RDNA 3 uses two types of chiplets: the Graphics Compute Die (GCD) and Memory Cache Dies (MCDs). On Ryzen and Epyc processors, AMD used its PCIe-based Infinity Fabric protocol with the package's dies connected via traces on an organic substrate. This approach is easily scalable in a cost-effective manner but has the drawbacks of increased latency, increased power consumption when moving data between dies at around 1.5 picojoules per bit, and it cannot achieve the connection density needed for high-bandwidth GPUs.<ref>{{cite web |last1=Walton |first1=Jarred |date=2023-06-05 |title=AMD RDNA 3 GPU Architecture Deep Dive: The Ryzen Moment for GPUs |url=https://www.tomshardware.com/news/amd-rdna-3-gpu-architecture-deep-dive-the-ryzen-moment-for-gpus#section-amd-rdna-3-and-gpu-chiplets |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref> An organic package could not host the number of wires that would be needed to connect multiple dies in a GPU.<ref>{{cite web |last1=Ridley |first1=Jacob |date=2022-11-14 |title=AMD's Infinity Links is the unsung hero of RDNA 3 and chiplet gaming GPUs |url=https://www.pcgamer.com/amd-infinity-links-rdna-3/ |website=PC Gamer |language=en-US |access-date=2026-05-31|url-status=live}}</ref> data

RDNA 3's dies are instead connected using TSMC's Integrated Fan-Out Re-Distribution Layer (InFO-RDL) packaging technique which provides a silicon bridge for high bandwidth and high density die-to-die communication.<ref name="TechPowerUp">{{Cite web |title=AMD Explains the Economics Behind Chiplets for GPUs |url=https://www.techpowerup.com/301071/amd-explains-the-economics-behind-chiplets-for-gpus |website=TechPowerUp |language=en-US |date=2022-11-14 |access-date=2026-05-31|url-status=live}}</ref> InFO allows dies to be connected without the use of a more costly silicon interposer such as the one used in AMD's Instinct MI200 and MI300 datacenter accelerators. Each Infinity Fanout link has 9.2 Gbps in bandwidth. Naffziger explains that "The bandwidth density that we achieve is almost 10x" with the Infinity Fanout rather than the wires used by Ryzen and Epyc processors. The chiplet interconnects in RDNA achieve cumulative bandwidth of 5.3{{nbsp}}TB/s.<ref name="TechPowerUp"/>

=== Memory Cache Dies (MCDs) === With a respective 2.05 billion transistors, each Memory Cache Die (MCD) contains 16{{nbsp}}MB of L3 cache. Theoretically, additional L3 cache could be added to the MCDs via AMD's 3D V-Cache die stacking technology as the MCDs contain unused TSV connection points.<ref>{{Cite web |last1=Klotz |first1=Aaron |date=2023-11-29 |title=AMD GPU Appears to Leave Room for Future 3D V-Cache |url=https://www.tomshardware.com/news/3d-vcache-rdna3-amd-gpu |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref><ref>{{Cite web |last1=Ridley |first1=Jacob |date=2023-01-30 |title=Tiny spots on AMD's RDNA 3 GPU hint at massive cache potential |url=https://www.pcgamer.com/tiny-spots-on-amds-rdna-3-gpu-hint-at-massive-cache-potential/ |website=PC Gamer |language=en-US |access-date=2026-05-31|url-status=live}}</ref> Also present on each MCD are two physical 32-bit GDDR6 memory interfaces for a combined 64-bit interface per MCD.<ref name="Walton">{{Cite web |last1=Walton |first1=Jarred |date=2022-11-14 |title=AMD RDNA 3 GPU Architecture Deep Dive: The Ryzen Moment for GPUs |url=https://www.tomshardware.com/news/amd-rdna-3-gpu-architecture-deep-dive-the-ryzen-moment-for-gpus |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref> The Radeon RX 7900 XTX has a 384-bit memory bus through the use of six MCDs while the RX 7900 XT has a 320-bit bus due to its five MCDs.

=== Graphics Compute Die (GCD) === ==== Compute Units ==== RDNA 3's Compute Units (CUs) for graphics processing are organized in dual CU Work Group Processors (WGPs). Rather than including a very large number of WGPs in RDNA 3 GPUs, AMD instead focused on improving per-WGP throughput. This is done with improved dual-issue shader ALUs with the ability to execute two instructions per cycle. It can contain up to 96 graphics Compute Units that can provide up to 61 TFLOPS of compute.<ref name="Gula">{{Cite web |last1=Gula |first1=Damien |date=2022-11-03 |title=AMD's RDNA 3 GPUs are Way Cheaper Than the RTX 4090 |url=https://gizmodo.com/amd-rdna-3-gpu-rtx-4090-4080-rx-7900-xtx-xt-price-date-1849741000 |website=Gizmodo |language=en-US |access-date=2026-05-31|url-status=live}}</ref>

While RDNA 3 include dedicated execution units for AI acceleration like the Matrix Cores found in AMD's compute-focused CDNA architectures, the efficiency of running inference tasks on FP16 execution resources is improved with Wave MMA (matrix multiply–accumulate) instructions. This results in increased inference performance compared to RDNA 2.<ref name="tomshw-rdna3">{{cite web |last1=Walton |first1=Jarred |title=AMD RDNA 3 and Radeon RX 7000-series GPUs: Everything we know |url=https://www.tomshardware.com/features/amd-radeon-rx-7000-rdna-3-price-performance-benchmarks-release-date#section-amd-rdna-3-architecture-ai-accelerators |website=Tom's Hardware |access-date=2026-05-31 |date=2024-06-15|url-status=live}}</ref><ref name="tomshw-interview">{{cite web |last1=Walton |first1=Jarred |last2=Alcorn |first2=Paul |title=Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger |url=https://www.tomshardware.com/features/gpu-chiplet-era-interview-amd-sam-naffziger |website=Tom's Hardware |access-date=2026-05-31 |date=2022-06-23 |quote=We asked whether AMD would include some form of tensor core or matrix core in the architecture, similar to what both Nvidia and Intel are doing with their GPUs. He responded that the split between RDNA and CDNA means stuffing a bunch of specialized matrix cores into consumer graphics products really isn't necessary for the target market, plus the FP16 support that already exists in previous RDNA architectures should prove sufficient for inference-type workloads.|url-status=live}}</ref> WMMA supports FP16, BF16, INT8, and INT4 data types.<ref name="wmma-gpuopen">{{cite web |last=Vasishta |first=Aaryaman |date=2026-05-31 |title=How to accelerate AI applications on RDNA 3 using WMMA |url=https://gpuopen.com/learn/wmma_on_rdna3/ |website=GPUOpen |language=en-US |access-date=2026-05-31 |archive-url=https://web.archive.org/web/20230110194947/https://gpuopen.com/learn/wmma_on_rdna3/ |url-status=live |archive-date=2023-01-10}}</ref> ''Tom's Hardware'' found that AMD's fastest RDNA 3 GPU, the RX 7900 XTX, was capable of generating 26 images per minute with Stable Diffusion, compared to only 6.6 images per minute of the RX 6950 XT, the fastest RDNA 2 GPU.<ref name="tomshw-sd">{{cite web |last1=Walton |first1=Jarred |title=Stable Diffusion Benchmarks: 45 Nvidia, AMD, and Intel GPUs Compared |url=https://www.tomshardware.com/pc-components/gpus/stable-diffusion-benchmarks |website=Tom's Hardware |access-date=2026-05-31 |date=2023-12-15|url-status=live}}</ref>

==== Ray tracing ==== RDNA 3 features second generation ray-tracing accelerators. Each Compute Unit contains one ray tracing accelerator. The overall number of ray tracing accelerators is increased due to the higher number of Compute Units, though the number of ray tracing accelerators per Compute Unit has not increased over RDNA 2.

==== Clock speeds ==== RDNA 3 was designed to support high clock speeds. On RDNA 3, clock speeds have been decoupled with the front end operating at a 2.5{{nbsp}}GHz frequency while the shaders operate at 2.3{{nbsp}}GHz. The shaders operating at a lower clock speed gives up to 25% power savings according to AMD and RDNA 3's shader clock speed is still 15% faster than RDNA 2.<ref>{{Cite web |last1=Olšan |first1=Jan |date=2022-11-07 |title=AMD RDNA 3 details: architecture changes, AI acceleration, DP 2.1 |url=https://www.hwcooling.net/en/amd-rdna-3-details-architecture-changes-ai-acceleration-dp-2-1-en/ |website=HWCooling |language=en-GB |access-date=2026-05-31|url-status=live}}</ref>

==== Cache and memory subsystem ==== RDNA 3 increased the capacity of L1 and L2 caches. The 16-way associative L1 cache shared across a shader array is doubled in RDNA 3 to 256{{nbsp}}KB. The L2 cache increased from 4{{nbsp}}MB on RDNA 2 to 6{{nbsp}}MB on RDNA 3. The L3 Infinity Cache has been lowered in capacity from 128{{nbsp}}MB to 96{{nbs}}MB and latency has increased as it is physically present on the MCDs rather than being closer to the WGPs within the GCD.<ref name="CAC">{{cite web |title=Microbenchmarking AMD's RDNA 3 Graphics Architecture |url=https://chipsandcheese.com/2023/01/07/microbenchmarking-amds-rdna-3-graphics-architecture/ |website=Chips and Cheese |language=en-US |date=2023-01-07 |access-date=2026-05-31}}</ref> The Infinity Cache capacity was decreased due to RDNA 3 having wider a memory interface up to 384-bit whereas RDNA 2 used memory interfaces up to 256-bit. RDNA 3 having a wider 384-bit memory means that its cache hitrate does not have to be as high to still avoid bandwidth bottlenecks as there is higher memory bandwidth.<ref name="CAC"/> RDNA 3 GPUs use GDDR6 memory rather than faster GDDR6X due to the latter's increased power consumption.

==== Media engine ==== RDNA 3 is the first RDNA architecture to have a dedicated media engine. It is built into the GCD and is based on VCN 4.0 encoding and decoding core.<ref>{{cite web |last1=Shilov |first1=Anton |date=2022-05-04 |title=First Details About AMD's Next Generation Video Engine Revealed |url=https://www.tomshardware.com/news/next-amd-video-engine-may-lack-av1 |website=Tom's Hardware |language=en-US |access-date=2026-05-31|url-status=live}}</ref> AMD's AMF AV1 encoder is comparable in quality to Nvidia's NVENC AV1 encoder but can handle a higher number of simultaneous encoding streams compared to the limit of 3 on the GeForce RTX 40 series.<ref>{{Cite web |last1=Klotz |first1=Aaron |date=2022-12-12 |title=AMD's Radeon RX 7900 AV1 encoder is almost on par with Intel Arc and Nvidia's RTX 40 series |url=https://www.techspot.com/news/96945-amd-radeon-rx-7900-av1-encoder-almost-par.html |website=TechSpot |language=en-US |access-date=2026-05-31|url-status=live}}</ref>

{| class="wikitable" style="text-align: center;" |+ Supported encoding frame rates (FPS) per resolution and video coding format<ref>{{Cite web |last1=Taylor |first1=Adam |date=2022-12-14 |title=Tested: With RDNA 3, AMD Radeon is finally useful for content creators |url=https://www.pcworld.com/article/1434166/amd-rdna-3-radeon-rx-7900-xtx-content-creation-review.html |website=PCWorld |language=en-US |access-date=2026-05-31|url-status=live}}</ref> |- ! Resolution ! H.264 ! H.265 ! AV1 |- ! style="text-align: left;" | {{resize|1080p60}} | 360 | 360 | 360 |- ! style="text-align: left;" | {{resize|1440p60}} | 360 | 360 | 360 |- ! style="text-align: left;" | {{resize|4K60}} | 180 | 180 | 240 |- ! style="text-align: left;" | {{resize|8K60}} | 48 | 48 | 60 |}

=== Display engine === RDNA 3 GPUs feature a new display engine called the "Radiance Display Engine". AMD touted its support for DisplayPort 2.1 UHBR 13.5, delivering up to 54Gbps bandwidth for high refresh rates at 4K and 8K resolutions.<ref>{{Cite web |last1=Sag |first1=Anshel |date=2022-11-14 |title=AMD's New Radeon RX 7900XTX And 7900XT Put The Pressure On NVIDIA |url=https://www.forbes.com/sites/moorinsights/2022/11/14/amds-new-radeon-rx-7900xtx-and-7900xt-put-the-pressure-on-nvidia/?sh=21776d571aa3 |website=Forbes |language=en-US |access-date=2026-05-31|url-status=live}}</ref> The Radeon Pro W7900 and W7800 support the 80Gbps UHBR20 standard. DisplayPort 2.1 can support 4K at 480{{nbsp}}Hz and 8K at 165{{nbsp}}Hz with Display Stream Compression (DSC). The previous DisplayPort 1.4 standard with DSC was limited to 4K at 240{{nbsp}}Hz and 8K at 60{{nbsp}}Hz.

=== Power efficiency === AMD claims that RDNA 3 achieves a 54% increase in performance-per-watt which is in line with their previous claims of 50% performance-per-watt increases for both RDNA and RDNA 2.

== Navi 3x dies == {| class="wikitable" style="text-align: center;" ! rowspan="2" colspan="3" | ! colspan="3" | Graphics Compute Die (GCD) ! rowspan="2" | Memory Cache Die (MCD) |- ! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-31.g998 Navi 31]<ref name="Walton" /> ! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-32.g1000 Navi 32]<ref>{{cite web | title=AMD RDNA 3 GPU Architecture Deep Dive: The Ryzen Moment for GPUs | date=2022-11-14 | url=https://www.tomshardware.com/news/amd-rdna-3-gpu-architecture-deep-dive-the-ryzen-moment-for-gpus |access-date=2026-05-31|website=Tom's Hardware|last=Walton|first=Jarred|url-status=live}}</ref> ! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-33.g1001 Navi 33] |- ! style="text-align: left;" colspan="3" | {{resize|Launch}} | {{dts|2022|December|13|format=my|abbr=on}} | {{dts|2023|September|06|format=my|abbr=on}} | {{dts|2023|January|04|format=my|abbr=on}} | {{dts|2022|December|13|format=my|abbr=on}} |- ! style="text-align: left;" colspan="3" | {{resize|Codename}} | ''Plum Bonito'' | ''Wheat Nas'' | ''Hotpink Bonefish'' | rowspan="2" {{NA}} |- ! style="text-align: left;" colspan="3" | {{resize|Compute units (Stream processors) [FP32 cores]}} | 96 (6144) [12288] | 60 (3840) [7680] | 32 (2048) [4096] |- ! style="text-align: left;" colspan="3" | {{resize|Process}} | colspan="2" | TSMC N5 | colspan="2" | TSMC N6 |- ! style="text-align: left;" colspan="3" | {{resize|Transistors}} | 45.4{{nbsp}}bn. | 28.1{{nbsp}}bn. | 13.3{{nbsp}}bn. | 2.05{{nbsp}}bn. |- ! style="text-align: left;" colspan="3" | {{resize|Transistor density}} | 150.2 MTr/mm2 | 143.4 MTr/mm2 | 65.2 MTr/mm2 | 54.64 MTr/mm2 |- ! style="text-align: left;" colspan="3" | {{resize|Die size}} | 304.35 mm2 | 196 mm2 | 204 mm2 | 37.52 mm2 |- ! style="text-align: left;" rowspan="4" | {{resize|Products}} ! style="text-align: left;" rowspan="2" | {{resize|Consumer}} ! style="text-align: left;" | {{resize|Desktop}} | {{ubl|RX 7900 GRE|RX 7900 XT|RX 7900 XTX}} | {{ubl|RX 7700 XT|RX 7800 XT}} | {{ubl|RX 7600|RX 7600 XT|RX 7650 GRE}} | {{ubl|RX 7700 XT (3×)|RX 7800 XT (4×)|RX 7900 GRE (4×)|RX 7900 XT (5×)|RX 7900 XTX (6×)}} |- ! style="text-align: left;" | {{resize|Mobile}} | {{ubl|RX 7900M}} | {{ubl|RX 7800M}} | {{ubl|RX 7600S|RX 7600M|RX 7600M XT|RX 7700S}} | {{ubl|RX 7900M (4×)}} |- ! style="text-align: left;" rowspan="2" | {{resize|Workstation}} ! style="text-align: left;" | {{resize|Desktop}} | {{ubl|W7800|W7900}} | {{ubl|W7700}} | {{ubl|W7500|W7600}} | {{ubl|W7700 (4×)|W7800 (4×)|W7900 (6×)}} |- ! style="text-align: left;" | {{resize|Mobile}} | {{NA}} | {{NA}} | {{NA}} | {{NA}} |- |}

== RDNA 3.5 Optimizations == At AI PC Innovation Summit in March 2024 AMD announced "Strix Point" codenamed CPUs <ref>{{Cite news |date=2024-03-22 |title=AMD Roadmaps Next-gen Ryzen "Strix Point" CPUs at AI PC Summit |url=https://www.techpowerup.com/320697/amd-roadmaps-next-gen-ryzen-strix-point-cpus-at-ai-pc-summit |url-status=live |archive-url=http://web.archive.org/web/20260227070058/https://www.techpowerup.com/320697/amd-roadmaps-next-gen-ryzen-strix-point-cpus-at-ai-pc-summit |archive-date=2026-02-27 |access-date=2026-05-31 |work=TechPowerUp |language=en}}</ref>. The announcement confirmed inclusion of "RDNA 3+" graphics technology in new onboard graphics on then-future Zen 5 processors.

In July 2024, AMD shared technical details about the optimizations in RDNA 3+, now called RDNA 3.5 <ref>{{cite web | last1=Evanson | first1=Nick | title=AMD's tweaked RDNA 3.5 GPU is solely focused on improving mobile gaming performance | work=PC Gamer | date=2024-07-18 | url=https://www.pcgamer.com/hardware/graphics-cards/amds-tweaked-rdna-35-gpu-is-solely-focused-on-improving-mobile-gaming-performance/ |access-date=2026-05-31|url-status=live}}</ref>. The reveal stated that the goal of RDNA 3.5 was to remove performance bottlenecks that AMD's GPUs come across when used in low-power configurations like laptops and handheld gaming PCs. The reveal presentation stated Strix Point achieved 19-32% higher performance at 15W compared to Hawk Point.

Compared to RDNA 3, the revised RDNA 3.5 doubles the per-cycle texel output from texture units housed in compute units. This compensates for lower core clock speeds used in low-power situations. Most rich vector shader instructions for interpolation and comparison are also double rate compared to RDNA 3. This increases performance per watt. Finally, LPDDR5 memory management is optimized with improved compression and batch processing to reduce costly memory accesses.

At CES 2025 in January 2025, AMD announced the Z2 series of processors <ref>{{cite web | title=AMD announces Ryzen Z2 series processors for handhelds — more performance, better efficiency, coming soon | date=2025-01-06 | url=https://www.tomshardware.com/pc-components/cpus/amd-announces-ryzen-z2-series-processors-for-handhelds-more-performance-better-efficiency-coming-soon |access-date=2026-05-31|website=Tom's Hardware|last=Walton|first=Jarred|url-status=live|language=en}}</ref>. This line-up included the Z2 Extreme, the first low-power CPU with integrated RDNA 3.5 graphics. At the same event, AMD announced the "Strix Halo" processors aimed at higher TDP <ref>{{cite web | title=AMD's beastly 'Strix Halo' Ryzen AI Max+ debuts with radical new memory tech to feed RDNA 3.5 graphics and Zen 5 CPU cores | date=2025-01-06 | url=https://www.tomshardware.com/pc-components/cpus/amds-beastly-strix-halo-ryzen-ai-max-debuts-with-radical-new-memory-tech-to-feed-rdna-3-5-graphics-and-zen-5-cpu-cores |access-date=2026-05-31|website=Tom's Hardware|last=Alcorn|first=Paul|url-status=live}}</ref>. Those also include RDNA 3.5 graphics with higher GPU core counts and base clocks.

== Products == === Gaming === ==== Desktop ==== {{AMD Radeon RX 7000}}

==== Mobile ==== {{AMD Radeon RX 7000M}}

=== Workstation === {{Main|Radeon Pro#Radeon Pro W7000 series|l1 = Radeon Pro W7000 series}} ==== Desktop workstation ==== {{AMD Radeon Pro W7000}}

=== Integrated graphics processing units (iGPUs) === {| class="wikitable" style="text-align: center; font-size: 85%; white-space:nowrap;" ! rowspan="2" | Model ! rowspan="2" | Launch ! rowspan="2" | Codename ! rowspan="2" | Architecture & fab ! rowspan="2" | Die size ! colspan="2" | Core ! colspan="2" | Fillrate{{efn|name="Boost"}}{{efn|name="Texture fill"}}{{efn|name="Pixel fill"}} ! colspan="3" | Processing power{{efn|name="Boost"}}{{efn|name="FLOPS"}} (GFLOPS) ! colspan="4" | Cache<ref>{{cite web | title=AMD's Radeon 890M: Strix Point's Bigger iGPU | url=https://chipsandcheese.com/p/amds-radeon-890m-strix-points-bigger-igpu |date=2024-08-24|access-date=2026-05-31|website=Chips and Cheese|last=Lam|first=Chester|url-status=live}}</ref><ref>{{cite web | title=Strix Halo's Memory Subsystem: Tackling iGPU Challenges | url=https://chipsandcheese.com/p/strix-halos-memory-subsystem-tackling |date=2025-10-31|access-date=2026-05-31|website=Chips and Cheese|last=Lam|first=Chester|url-status=live|language=en}}</ref> !Memory ! rowspan="2" | TDP |- ! Config{{efn|name="Core config"}}{{efn|name="Stream processors"}} ! style="width:4em;" | Clock{{efn|name="Boost"}} (MHz) ! Texture (GT/s) ! Pixel (GP/s) ! style="width:4em;" | Half [FP16] ! style="width:4em;" | Single [FP32] ! style="width:4em;" | Double [FP64] ! style="width:4em;" | L0 ! style="width:4em;" | L1 ! style="width:4em;" | L2 !L3 !Bus type & width |- ! colspan="18" |RDNA 3

|- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/apu/amd-ryzen-5-7540u Radeon 740M] | rowspan="3" | {{dts|2023|April|format=mdy|abbr=on}} | rowspan="5" | Phoenix Hawk Point | rowspan="5" | RDNA 3 TSMC{{nbsp}}N4 | rowspan="5" | 178{{nbsp}}mm2 | 4 CUs 256:16:8:4 | 2,500 | 40.0 | 20.0 | 5,120 | 2,560 | 80.0 | 192{{nbsp}}KB | rowspan="5" | 512{{nbsp}}KB | rowspan="5" | 2{{nbsp}}MB | rowspan="5" |NA | rowspan="3" |DDR5 / LPDDR5(X) 128-bit | 15–30{{nbsp}}W |-

! style="text-align:left; height:3em;" | {{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-5-7640hs Radeon 760M]}} | 8 CUs 512:32:16:8 | 2,600 | 83.2 | 41.6 | 10,650 | 5,325 | 166.4 | 384{{nbsp}}KB | rowspan="2" | 15–65{{nbsp}}W |-

! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/apu/amd-ryzen-9-7940hs Radeon 780M] | 12 CUs <ref>{{Cite web |date=2025-05-27 |title=Radeon 780M: Full Guide to AMD’s New Integrated Graphics |url=https://www.geekompc.com/radeon-780m/ |url-status=live |access-date=2026-05-31 |website=Geekom |language=en-US}}</ref> 768:48:24:12 | 2,800 | 134.4 | 67.2 | 17,203 | 8,602 | 268.8 | 1.125{{nbsp}}MB |-

! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/apu/amd-ryzen-z1 Ryzen Z1] | rowspan="2" | {{dts|2023|June|13|format=mdy|abbr=on}} | 4 CUs 256:16:8:4 | 2,500 | 40.0 | 20.0 | 5,120 | 2,560 | 80.0 | 192{{nbsp}}KB | rowspan="2" |LPDDR5(X) 128-bit | rowspan="2" | 9–30{{nbsp}}W |-

! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/apu/amd-ryzen-z1-extreme Ryzen Z1 Extreme] | 12 CUs 768:48:24:12 | 2,800 | 134.4 | 67.2 | 17,203 | 8,602 | 268.8 | 1.125{{nbsp}}MB

|- ! colspan="18" |RDNA 3.5

|- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/300-series/amd-ryzen-ai-9-365.html Radeon 880M] | rowspan="2" | {{dts|2024|July|format=mdy|abbr=on}} | rowspan="2" | Strix Point | rowspan="8" | RDNA 3.5 TSMC{{nbsp}}N4P | rowspan="2" | 232.5{{nbsp}}mm2 | 12 CUs 768:48:24:12 | 2,900 | 139.2 | 69.6 | 17,818 | 8,909 | 278.4 | 1.125{{nbsp}}MB | rowspan="8" | 512{{nbsp}}KB | rowspan="8" | 2{{nbsp}}MB | rowspan="5" |NA | rowspan="5" |DDR5 / LPDDR5(X) 128-bit | rowspan="5" | 15–54{{nbsp}}W

|- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/300-series/amd-ryzen-ai-9-hx-375.html Radeon 890M] | 16 CUs 1024:64:32:16 | 2,900 | 185.6 | 92.8 | 23,757 | 11,878 | 371.2 | 1.5{{nbsp}}MB |- ! style="text-align: left;" |Radeon 820<ref>{{Cite web |title=AMD Ryzen™ AI 5 330 |url=https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-5-330.html |access-date=2026-05-31 |website=AMD|url-status=live}}</ref>M |Jan 2025 |Kraken point | |2 CUs 128:8:4:2 |2800 | | | | | | |- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-5-340.html Radeon 840M] | rowspan="5" |Jan 2025 | rowspan="2" |Krackan Point | rowspan="2" | | 4 CUs 256:16:8:4 | 2,900 | 46.4 | 23.3 | 5,939 | 2,969 | 92.8 | 192{{nbsp}}KB |- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-7-350.html Radeon 860M] | 8 CUs 512:32:16:8 | 3,000 | 96 | 48 | 12,288 | 6,144 | 192 | 384{{nbsp}}KB |- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-max-pro-300-series/amd-ryzen-ai-max-pro-380.html Radeon 8040S] | rowspan="3" |Strix Halo | 233 mm2 | 16 CUs 1024:64:32:16 | 2,800 | 179.2 | 89.6 | 22,937 | 11,468 | 358 | 1.5 MB | rowspan="3" |32 MB | rowspan="3" |LPDDR5X 256-bit | rowspan="3" |45-120 W |- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-390.html Radeon 8050S] | rowspan="2" | 308{{nbsp}}mm2 | 32 CUs 2048:128:64:32 | 2,800 | 358.4 | 179.2 | 45,875 | 22,937 | 716 | 3 MB |- ! style="text-align:left; height:3em;" | [https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-plus-395.html Radeon 8060S] | 40 CUs 2560:160:80:40 | 2,900 | 464 | 232 | 59,392 | 29,696 | 928 | 3.75 MB |} {{notelist|refs= {{efn|name="Boost"|Boost values (if available) are stated below the base value in ''italic''.}} {{efn|name="Texture fill"|Texture fillrate is calculated as the number of '''Texture Mapping Units''' multiplied by the base (or boost) core clock speed.}} {{efn|name="Pixel fill"|Pixel fillrate is calculated as the number of '''Render Output Units''' multiplied by the base (or boost) core clock speed.}} {{efn|name="FLOPS"|Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.}} {{efn|name="Core config"|Compute Units (CUs) Stream Processors : Texture mapping units : Render output units : Ray accelerators}} {{efn|name="Stream processors"|GPUs based on RDNA 3 have dual-issue '''stream processors''' so that up to two shader instructions can be executed per clock cycle under certain parallelism conditions.}} }}

== References == {{reflist}}

Category:AMD microarchitectures Category:Computer-related introductions in 2022 Category:Graphics microarchitectures