{{Short description|Type of computer processor}} {{primary sources|date=October 2015}}
A '''wide-issue''' architecture is a computer processor that issues more than one instruction per clock cycle.<ref>{{cite web|title=Scheduling for Superscalar & Multiple Issue Machines|url=http://pages.cs.wisc.edu/~fischer/cs701.f08/lectures/Lecture12.4up.pdf}}</ref> They can be considered in three broad types:
* Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle. * VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.<ref>{{cite web|title=Wide Issue and Speculation|url=http://taco.cse.tamu.edu/utsa-www/cs5513-fall07/lecture6.html|access-date=2015-10-23|archive-date=2016-03-04|archive-url=https://web.archive.org/web/20160304142831/http://taco.cse.tamu.edu/utsa-www/cs5513-fall07/lecture6.html|url-status=dead}}</ref> * Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.<ref>{{cite web|last1=Martin|first1=Milo|title=Superscalar|url=https://www.cis.upenn.edu/~milom/cis501-Fall11/lectures/07_superscalar.pdf|access-date=2015-10-30|archive-date=2021-10-09|archive-url=https://web.archive.org/web/20211009184454/https://www.cis.upenn.edu/~milom/cis501-Fall11/lectures/07_superscalar.pdf|url-status=dead}}</ref>
==See also== *Out-of-order execution *Explicitly parallel instruction computing
==References== {{Reflist}}
Category:Instruction processing Category:Parallel computing
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