{{Short description|Microprocessor functions outside of, but closely connected to, the core}} {{Update|date=January 2017}} "'''Uncore'''" is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance. It was introduced with the Nehalem microarchitecture.<ref name="modular uncore">{{cite web|url=http://www.intel.com/technology/ITJ/2010/v14i3/ITJ10_3_2_The-Uncore.htm |title=Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel |publisher=Intel.com |date= |accessdate=2014-01-21}}</ref> It has been called "'''system agent'''" since the release of the Sandy Bridge microarchitecture.<ref name="sandybridge">{{cite web | url=http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4 | archive-url=https://web.archive.org/web/20100916181911/http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4 | url-status=dead | archive-date=September 16, 2010 | title=Intel's Sandy Bridge Architecture Exposed | publisher=AnandTech | date=September 14, 2010 | accessdate=July 15, 2015 | author=Anand Lal Shimpi}}</ref>
The Uncore/SA handles the functionalities traditionally assigned to the northbridge: QPI controllers, L3 cache, snoop agent pipeline, on-die memory controller, on-die PCI Express Root Complex, and Thunderbolt controller.<ref name="thunderbolt">{{cite web|url=http://www.intel.com/technology/io/thunderbolt/ |title=Thunderbolt™ Technology for Developers |publisher=Intel.com |date=2014-01-13 |accessdate=2014-01-21}}</ref> Integration of these functions into the core makes them physically closer, thereby reducing their access latency. In contrast, the "core" (processor) component consists of the control unit, ALU, FPU, and L1 and L2 caches.<ref name="Anandtech: Nehalem: The Unwritten Chapters"/> Other bus controllers such as SPI and LPC are part of the chipset (Platform Controller Hub), the equivalent of the southbridge.<ref name="Anandtech: Nehalem: The Unwritten Chapters">{{cite web|url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3453 |archive-url=https://web.archive.org/web/20090601070316/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3453 |url-status=dead |archive-date=June 1, 2009 |title=Nehalem: The Unwritten Chapters |publisher=AnandTech |date= |accessdate=2014-01-21}}</ref> Further integration has since eliminated the PCH from the motherboard for a system-in-package design on mobile SKUs.<ref>{{Cite web|url=https://www.anandtech.com/show/8814/intel-releases-broadwell-u-new-skus-up-to-48-eus-and-iris-6100|archive-url=https://web.archive.org/web/20150107170617/http://anandtech.com/show/8814/intel-releases-broadwell-u-new-skus-up-to-48-eus-and-iris-6100|url-status=dead|archive-date=January 7, 2015|title=Intel Releases Broadwell-U: New SKUs, up to 48 EUs and Iris 6100|first=Ian|last=Cutress|website=www.anandtech.com}}</ref>
==Parts== Specifically, the microarchitecture of the Nehalem-EX uncore is broken down into a number of modular units. The main uncore interface to the core is the so-called cache box (CBox), which interfaces with the last level cache (LLC) and is responsible for managing cache coherency. Multiple internal and external QPI links are managed by physical-layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMCs (MBox) are managed by the system configuration controller (UBox) and a router (RBox).<ref name="Uncore Programming Guide">{{cite web|url=http://www.intel.com/Assets/PDF/designguide/323535.pdf |title=Intel(R) Xeon(R) Processor 7500 Series Uncore Programming Guide |date= |accessdate=2014-01-30}}</ref>
Removal of serial bus controllers from the Intel uncore further enables increased performance by allowing the uncore clock (UCLK) to run at a base of 2.66 GHz, with overclocking limits in excess of 3.44 GHz.<ref name="UCLK">{{cite web|last=Yus |first=Carlos |url=https://highperformancesystems.blogspot.com/2011/01/intel-sandy-bridge-out-of-specification.html |title=HighPerformanceSystems: Intel Sandy Bridge out of specification 4.0, 4.4 and 4.6 GHz. Updated – HighPerformanceSystems |publisher=Highperformancesystems.blogspot.com |date=2011-01-27 |accessdate=2014-01-21|quote=Also remember that in this test Nehalem has a Uncore and L3 cache frequency increased to 3.44 GHz from 2.66 GHz nominal, which helps greatly. }}</ref> This increased clock rate allows the core to access critical functions (such as the IMC) with significantly less latency, typically reducing core access times to DRAM by 10 ns or more.
== References == {{Reflist|30em}}
=== Additional references === "Thunderbolt™ Technology for Developers." Intel.com. Retrieved March 30, 2025.
Anand Lal Shimpi, "Intel's Sandy Bridge Architecture Exposed," AnandTech, September 14, 2010; updated information available in later reviews of later architectures.
"Intel® Xeon® Processor Uncore Programming Guide." Intel.com. Retrieved March 2025.
== External links == * [http://www.intel.com/products/processor/manuals/ Intel Software Developer's Manual. Vol. 3A & 3B]
Category:Microprocessors