A '''trap flag''' permits operation of a processor in single-step mode. If such a flag is available, debuggers can use it to step through the execution of a computer program.<ref>{{cite book |url=https://bitsavers.org/pdf/dec/pdp11/handbooks/PDP-1120_Handbook_1972.pdf |title=Processor Handbook PDP-11/20/15/R20 |page=11 |publisher=Digital Equipment Corporation |date=1971}}</ref><ref>{{Cite web |title=Intel 64 and IA-32 Architectures Software Developer's Manual |url=https://cdrdv2-public.intel.com/835781/325462-sdm-vol-1-2abcd-3abcd-4.pdf |url-status=live |archive-url=https://web.archive.org/web/20241109055756/https://cdrdv2-public.intel.com/835781/325462-sdm-vol-1-2abcd-3abcd-4.pdf |archive-date=November 9, 2024 |access-date=November 15, 2024}}</ref>
The trap flag, when set, causes the machine to trap after executing one instruction. The trap handler can cause a debugger to be notified; the debugger can then inspect the contents of registers and memory locations and either continue or stop and let the user of the debugger examine additional data in the program.
==References== {{Reflist}}
Category:Central processing unit Category:Debugging