{{Short description|Component of a computer's processor}} {{Use dmy dates|date=March 2020|cs1-dates=y}} {{Broader|Stack (abstract data type)#Basic architecture of a stack|Call stack#Structure|topic=stack pointers}}
A '''stack register''', also known as a '''stack pointer''', is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register. On a machine with multiple general-purpose registers, it may be a register that is reserved by convention, such as on the IBM System/360 through z/Architecture architecture and RISC architectures, or it may be a register that procedure call and return instructions are hardwired to use, such as on the PDP-11, VAX, and Intel x86 architectures. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function.
Machines before the late 1960s—such as the PDP-8 and HP 2100—did not have compilers which supported recursion. Their subroutine instructions typically would save the current location in the jump address, and then set the program counter to the ''next'' address.<ref name="Salomon_1993"/> While this is simpler than maintaining a stack, since there is only one return location per subroutine code section, there cannot be recursion without considerable effort on the part of the programmer.
A stack machine may have 2 or more stack registers — one of them keeps track of a call stack, the other(s) keep track of other stack(s).
== Stack engine == Simpler processors store the stack pointer in a regular hardware register and use the arithmetic logic unit (ALU) to manipulate its value. In processors with instructions that push items onto the stack and pop items from the stack, those instructions are either executed with multiple hardwired CPU cycles or microinstructions or are translated into multiple micro-ops, to separately add/subtract the stack pointer, and perform the load/store in memory.<ref name="Stokes_2004"/>
Newer processors of that type contain a dedicated '''stack engine''' to optimize stack operations. Pentium M was the first x86 processor to introduce a stack engine. In its implementation, the stack pointer is split among two registers: ESP<sub>O</sub>, which is a 32-bit register, and ESP<sub>d</sub>, an 8-bit delta value that is updated directly by stack operations. PUSH, POP, CALL and RET opcodes operate directly with the ESP<sub>d</sub> register. If ESP<sub>d</sub> is near overflow or the ESP register is referenced from other instructions (when ESP<sub>d</sub> ≠ 0), a synchronisation micro-op is inserted that updates the ESP<sub>O</sub> using the ALU and resets ESP<sub>d</sub> to 0. This design has remained largely unmodified in later Intel processors, although ESP<sub>O</sub> has been expanded to 64 bits.<ref name="Fog"/>
A stack engine similar to Intel's was also adopted in the AMD K8 microarchitecture. In Bulldozer, the need for synchronization micro-ops was removed, but the internal design of the stack engine is not known.<ref name="Fog"/>
== References == <references> <ref name="Salomon_1993">{{cite book |author-first=David |author-last=Salomon |editor-first=Ian D. |editor-last=Chivers |title=Assemblers and Loaders |date=February 1993 |orig-year=1992 |edition=1 |series=Ellis Horwood Series In Computers And Their Applications |publisher=Ellis Horwood Limited / Simon & Schuster International Group |location=California State University, Northridge, California, USA |publication-place=Chicester, West Sussex, UK |isbn=0-13-052564-2 |url=http://www.davidsalomon.name/assem.advertis/asl.pdf |access-date=2008-10-01 |url-status=live |archive-url=https://web.archive.org/web/20200323010358/http://www.davidsalomon.name/assem.advertis/asl.pdf |archive-date=2020-03-23 |quote=Most computers save the return address in either the stack, in one of the registers, or in the first word of the procedure (in which case the first executable instruction of the procedure should be stored in the second word). If the latter method is used, a return from the procedure is a jump to the memory location whose address is contained in the first word of the procedure.}} (xiv+294+4 pages)</ref> <ref name="Stokes_2004">{{Cite web |url=http://archive.arstechnica.com/cpu/004/pentium-m/m-pentium-m-5.html |title=A Look at Centrino's Core: The Pentium M |author-first=Jon "Hannibal" |author-last=Stokes |date=2004-02-25 |website=archive.arstechnica.com |page=5}}</ref> <ref name="Fog">{{Cite web |url=http://www.agner.org/optimize/microarchitecture.pdf |title=The microarchitecture of Intel, AMD and VIA CPUs |author-last=Fog |author-first=Agner |publisher=Technical University of Denmark }}</ref> </references>
{{CPU technologies}}
Category:Control flow Category:Central processing unit Category:Digital registers