{{Short description|Microprocessor design embeddable in other computer systems}} {{Use American English|date = April 2019}} {{missing information||three OpenPOWER cores, one Moxie core, both at RTL level|date=July 2020}} A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., FPGA, CPLD), including both high-end and commodity variations.<ref>{{usurped|1=[https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html Article title]}} "Zet soft core running Windows 3.0" by Andrew Felch 2011</ref>

Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.<ref> {{cite web |url=http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |title=Embedded.com - FPGA Architectures from 'A' to 'Z' : Part 2 |access-date=2012-08-18 |url-status=dead |archive-url=https://web.archive.org/web/20071008163016/http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |archive-date=2007-10-08 }} "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006 </ref> In those multi-core systems, rarely used resources can be shared between all the cores in a cluster.

While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is limited only by the size of the FPGA.<ref>[http://www.xilinx.com/products/design_resources/proc_central/microblaze_faq.pdf MicroBlaze Soft Processor: Frequently Asked Questions] {{webarchive|url=https://web.archive.org/web/20111027074459/http://www.xilinx.com/products/design_resources/proc_central/microblaze_faq.pdf |date=2011-10-27 }}</ref> Some people have put dozens or hundreds of soft microprocessors on a single FPGA.<ref> István Vassányi. "Implementing processor arrays on FPGAs". 1998. [https://doi.org/10.1007%2FBFb0055278 ] </ref><ref> Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". [http://www.design-reuse.com/articles/21583/processor-noc-fpga.html] </ref><ref> John Kent. "Micro16 Array - A Simple CPU Array" [http://members.optusnet.com.au/jekent/Micro16Array/index.html] </ref><ref> Kit Eaton. "1,000 Core CPU Achieved: Your Future Desktop Will Be a Supercomputer". 2011. [http://www.fastcompany.com/1714174/1000-core-cpu-achieved-your-future-desktop-will-be-a-supercomputer?partner=rss] </ref><ref> "Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [http://www.ecnmag.com/news/2011/01/research/Over-1000-Cores-on-One-Chip.aspx] {{Webarchive|url=https://web.archive.org/web/20120305082424/http://www.ecnmag.com/news/2011/01/research/Over-1000-Cores-on-One-Chip.aspx |date=2012-03-05 }} </ref> This is one way to implement massive parallelism in computing and can likewise be applied to in-memory computing.

A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.<ref>{{Cite web | author=Joe DeLaere. | url=https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01255-top-7-reasons-to-replace-your-microcontroller-with-a-max-10-fpga.pdf | title="Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA"}} </ref><ref>{{Cite web |author1=John Swan |author2=Tomek Krzyzak. | url=http://www.embedded.com/print/4015159 | title="Using FPGAs to avoid microprocessor obsolescence" | date=2008 | archive-url=https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159 | archive-date=2016-10-13 }}</ref><ref> {{Cite web|url=https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/|title=FPGA processor IP needs to be supported|last=Staff|date=2010-02-03|website=Electronics Weekly|language=en-GB|access-date=2019-04-03}} </ref>

== Core comparison ==

{| class="wikitable sortable" |- ! Processor ! Developer ! Open source ! Bus support ! Notes ! Project home ! Description language |- | colspan="7" align="center" | ''based on the ARM instruction set architecture'' |- | Amber | Conor Santifort | {{yes|LGPLv2.1}} | Wishbone | ARMv2a 3-stage or 5-stage pipeline | [https://opencores.org/project/amber Project page at Opencores] | Verilog |- | Cortex-M1 | ARM | {{no}} | [http://www.arm.com/products/system-ip/interconnect/index.php] | 70–200{{nbsp}}MHz, 32-bit RISC | [http://www.arm.com/products/CPUs/ARM_Cortex-M1.html] | Verilog |- | colspan="7" align="center" | ''based on the AVR instruction set architecture'' |- | Navré | Sébastien Bourdeauducq | {{yes}} | Direct SRAM | Atmel AVR-compatible 8-bit RISC | [http://opencores.org/project,navre Project page at Opencores] | Verilog |- | pAVR | Doru Cuturela | {{yes}} | | Atmel AVR-compatible 8-bit RISC | [http://opencores.org/project,pavr Project page at Opencores] | VHDL |- | softavrcore | Andras Pal | {{yes}} | Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM) | Atmel AVR-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included | [http://opencores.org/project/softavrcore Project page at Opencores] | Verilog |- | colspan="7" align="center" | ''based on the MicroBlaze instruction set architecture'' |- | AEMB | Shawn Tan | {{yes}} | Wishbone | MicroBlaze EDK 3.2 compatible | [http://www.aeste.my/aemb AEMB] | Verilog |- | MicroBlaze | Xilinx | {{no}} | PLB, OPB, FSL, LMB, AXI4 | | [https://web.archive.org/web/20030430214925/http://www.xilinx.com/microblaze/ Xilinx MicroBlaze] | |- | OpenFire | Virginia Tech CCM Lab | {{yes}} | OPB, FSL | Binary compatible with the MicroBlaze | [https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html]<ref>{{Cite web|url=http://opencores.org/project,openfire_core,overview|title=Overview :: OpenFire Processor Core :: OpenCores}}</ref> | Verilog |- | SecretBlaze | LIRMM, University of Montpellier / CNRS | {{yes}} | Wishbone | MicroBlaze ISA, VHDL | [http://www.lirmm.fr/ADAC/?page_id=462 SecretBlaze] | VHDL |- | colspan="7" align="center" | ''based on the MCS-51 instruction set architecture'' |- | [http://www.microcorelabs.com MCL51] | MicroCore Labs | {{yes}} | Ultra-small-footprint microsequencer-based 8051 core | 312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs. | [http://www.microcorelabs.com MCL51 Core] | |- | [https://web.archive.org/web/20131008041359/http://wiki.altium.com/display/ADOH/TSK51x+MCU TSK51/52] | Altium | {{no|Royalty-free}} | Wishbone / Intel 8051 | 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative | [https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design Embedded Design on Altium Wiki] | |- | colspan="7" align="center" | ''based on the MIPS instruction set architecture'' |- | [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ BERI] | University of Cambridge | {{yes|BSD}} | | MIPS | [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Project page] | Bluespec |- | [http://www.dossmatik.de/mais-cpu.html Dossmatik] | René Doss | {{yes|CC BY-NC 3.0, except ''commercial applicants have to pay a licence fee''.}} | Pipelined bus | MIPS I instruction set pipeline stages | [http://www.dossmatik.de/mais-cpu.html Dossmatik] | VHDL |- | [https://web.archive.org/web/20131020113429/http://wiki.altium.com/display/ADOH/TSK3000A TSK3000A] | Altium | {{no|Royalty-free}} | Wishbone | 32-bit R3000-style RISC modified Harvard-architecture CPU | [https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design Embedded Design on Altium Wiki] | |- | colspan="7" align="center" | ''based on the PicoBlaze instruction set architecture'' |- | PacoBlaze | Pablo Bleyer | {{yes}} | | Compatible with the PicoBlaze processors | [http://bleyer.org/pacoblaze PacoBlaze] | Verilog |- | PicoBlaze | Xilinx | {{no}} | | | [https://web.archive.org/web/20030501203653/http://www.xilinx.com/picoblaze/ Xilinx PicoBlaze] | VHDL, Verilog |- | colspan="7" align="center" | ''based on the RISC-V instruction set architecture'' |- | [https://github.com/f32c/f32c f32c] | University of Zagreb | {{yes|BSD}} | AXI, SDRAM, SRAM | 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain | [https://github.com/f32c/f32c f32c] | VHDL |- | [https://github.com/stnolting/neorv32 NEORV32] | Stephan Nolting | {{yes|BSD}} | Wishbone b4, AXI4 | rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain | [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores] | VHDL |- | VexRiscv | SpinalHDL|SpinalHDL | {{Yes}} | AXI4 / Avalon | 32-bit, RISC-V, up to 340{{nbsp}}MHz on Artix 7. Up to 1.44{{nbsp}}DMIPS/MHz. | https://github.com/SpinalHDL/VexRiscv | VHDLVerilog (SpinalHDL) |- | colspan="7" align="center" | ''based on the SPARC instruction set architecture'' |- | LEON2(-FT) | ESA | {{yes}} | AMBA2 | SPARC V8 | [http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html ESA] | VHDL |- | LEON3/4 | Aeroflex Gaisler | {{yes}} | AMBA2 | SPARC V8 | [http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=156&Itemid=104 Aeroflex Gaisler] | VHDL |- | [http://parallel.princeton.edu/openpiton/specs.html OpenPiton] | Princeton Parallel Group | {{Yes}} | | Manycore SPARC V9 | [http://parallel.princeton.edu/openpiton/specs.html OpenPiton] | Verilog |- | OpenSPARC T1 | Sun | {{yes}} | | 64-bit | [http://www.opensparc.net/opensparc-t1/index.html OpenSPARC.net] | Verilog |- | Tacus/PIPE5 | TemLib | {{yes}} | Pipelined bus | SPARC V8 | [http://temlib.org TEMLIB] | VHDL |- | colspan="7" align="center" | ''based on the x86 instruction set architecture'' |- | CPU86 | HT-Lab | {{yes}} | | 8088-compatible CPU in VHDL | [http://www.ht-lab.com/cpu86.htm cpu86] | VHDL |- | [http://www.microcorelabs.com MCL86] | MicroCore Labs | {{yes}} | 8088 BIU provided. Others easy to create. | Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7. | [http://www.microcorelabs.com MCL86 Core] | |- | [https://www.jamieiles.com/80186/ s80x86] | Jamie Iles | {{yes|GPLv3}} | Custom | 80186-compatible GPLv3 core | [https://www.jamieiles.com/80186/ s80x86] | SystemVerilog |- | Zet | Zeus Gómez Marmolejo | {{yes}} | Wishbone | x86 PC clone | [https://archive.today/20130112150552/http://zet.aluzina.org/ Zet] | Verilog |- | ao486 | Aleksander Osman | {{yes|3-Clause BSD}} | Avalon | i486 SX compatible core | [https://github.com/alfikpl/ao486 ao486] | Verilog |- | colspan="7" align="center" | ''based on the PowerPC/Power instruction set architecture'' |- | PowerPC 405S | IBM | {{No}} | CoreConnect | 32-bit PowerPC v.2.03 Book E | IBM | Verilog |- | PowerPC 440S | IBM | {{No}} | CoreConnect | 32-bit PowerPC v.2.03 Book E | IBM | Verilog |- | PowerPC 470S | IBM | {{No}} | CoreConnect | 32-bit PowerPC v.2.05 Book E | IBM | Verilog |- | Microwatt | IBM/OpenPOWER | {{yes|CC-BY 4.0}} | Wishbone | 64-bit PowerISA 3.0 proof of concept | [https://github.com/antonblanchard/microwatt Microwatt @ Github] | VHDL |- | Chiselwatt | IBM/OpenPOWER | {{yes|CC-BY 4.0}} | Wishbone | 64-bit PowerISA 3.0 | [https://github.com/antonblanchard/chiselwatt Chiselwatt @ Github] | Chisel |- | Libre-SOC | [https://libre-soc.org Libre-SoC.org] | {{yes|BSD/LGPLv2+}} | Wishbone | 64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions | [https://libre-soc.org Libre-SoC.org] | python/nMigen |- | A2I | IBM/OpenPOWER | {{yes|CC-BY 4.0}} | Custom PBus | 64-bit PowerPC 2.6 Book E. In order core | [https://github.com/openpower-cores/a2i A2I @ Github] | VHDL |- | A2O | IBM/OpenPOWER | {{yes|CC-BY 4.0}} | Custom PBus | 64-bit PowerPC 2.7 Book E. Out of order core | [https://github.com/openpower-cores/a2o A2O @ Github] | Verilog |- | colspan="7" align="center" | ''Other architectures'' |- | ARC | ARC International, Synopsys | {{no}} | | 16/32/64-bit ISA RISC | [https://www.synopsys.com/designware-ip/processor-solutions.html DesignWare ARC] | Verilog |- | ERIC5 | Entner Electronics | {{no}} | | 9-bit RISC, very small size, C-programmable | [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5] {{Webarchive|url=https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html |date=2016-03-05 }} | VHDL |- | [https://github.com/howerj/forth-cpu H2 CPU] | Richard James Howe | {{yes | MIT}} | Custom | 16-bit Stack Machine, designed to execute Forth directly, small | [https://github.com/howerj/forth-cpu H2 CPU] | VHDL |- | [http://www.fpga-cores.com/instant-soc/ Instant SoC] | [http://www.fpga-cores.com/ FPGA Cores] | {{no}} | Custom | 32-bit RISC-V M Extension, SoC defined by C++ | [http://www.fpga-cores.com/instant-soc/ Instant SoC] | VHDL |- | JOP | Martin Schoeberl | {{yes}} | SimpCon / Wishbone (extension) | Stack-oriented, hard real-time support, executing Java bytecode directly | [https://web.archive.org/web/20190417225405/http://www.jopdesign.com/ Jop] | VHDL |- | LatticeMico8 | Lattice | {{yes}} | Wishbone | | [http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx LatticeMico8] | Verilog |- | LatticeMico32 | Lattice | {{yes}} | Wishbone | | [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm LatticeMico32] | Verilog |- | [https://lxp32.github.io/ LXP32] | Alex Kuznetsov | {{yes|MIT}} | Wishbone | 32-bit, 3-stage pipeline, register file based on block RAM | [https://lxp32.github.io/ lxp32] | VHDL |- | [https://github.com/MicroCoreLabs/Projects MCL65] | MicroCore Labs | {{yes}} | Ultra-small-footprint microsequencer-based 6502 core | 252 Spartan-7 LUTs. Clock cycle-exact. | [https://github.com/MicroCoreLabs/Projects MCL65 Core] | |- | [https://mrisc32.bitsnbites.eu/ MRISC32-A1] | Marcus Geelnard | {{yes}} | Wishbone, B4/pipelined | 32-bit RISC/Vector CPU implementing the MRISC32 ISA | [https://mrisc32.bitsnbites.eu/ MRISC32] | VHDL |- | [https://github.com/stnolting/neo430 NEO430] | Stephan Nolting | {{yes}} | Wishbone (Avalon, AXI4-Lite) | 16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable | [https://github.com/stnolting/neo430 NEO430] | VHDL |- | Nios, Nios II | Altera | {{no}} | Avalon | | [https://web.archive.org/web/20101225092752/http://www.altera.com/products/ip/processors/nios2/ni2-index.html Altera Nios II] | Verilog |- | OpenRISC | OpenCores | {{yes}} | Wishbone | 32-bit; done in ASIC, Actel, Altera, Xilinx FPGA. | [https://openrisc.io/] | Verilog |- | SpartanMC | TU Darmstadt / TU Dresden | {{Yes}} | Custom (AXI support in development) | 18-bit ISA (GNU Binutils / GCC support in development) | [http://www.spartanmc.de SpartanMC] | Verilog |- | SYNPIC12 | Miguel Angel Ajo Pelayo | {{yes|MIT}} | | PIC12F compatible, program synthesised in gates | [http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core nbee.es] | VHDL |- | xr16 | Jan Gray | {{no}} | XSOC abstract bus | 16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118 | [http://www.fpgacpu.org/xsoc/index.html XSOC/xr16] | Schematic |- | YASEP | Yann Guidon | {{yes|AGPLv3}} | Direct SRAM | 16 or 32 bits, RTL in [https://web.archive.org/web/20121207045204/http://yasep.org/VHDL/ VHDL] & [http://yasep.org/#!ASM/impASM#examples/keywords.yas asm] in JS, microcontroller subset : ready | [http://yasep.org yasep.org] ([http://www.mozilla.com/ Firefox] required) | VHDL |- | [http://zipcpu.com/about/zipcpu.html ZipCPU] | [http://zipcpu.com/about/gisselquist-technology.html Gisselquist Technology] | {{yes|GPLv3}} | Wishbone, B4/pipelined | 32-bit CPU targeted for minimal FPGA resource usage | [http://zipcpu.com/about/zipcpu.html zipcpu.com] | Verilog |- | ZPU | Zylin AS | {{yes}} | Wishbone | Stack based CPU, configurable 16/32 bit datapath, eCos support | [http://opensource.zylin.com/zpu.htm Zylin CPU] | VHDL |- |RISC5 |Niklaus Wirth| Niklaus Wirth | {{yes}} |Custom |Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board. |[http://www.projectoberon.com/ www.projectoberon.com/] |Verilog |}

== See also == * System-on-a-chip (SoC) ** Network-on-a-chip (NoC) * Reconfigurable computing ** Field-programmable gate array (FPGA) * VHDL * Verilog ** SystemVerilog * Hardware acceleration

==References== {{Reflist}}<!--added above External links/Sources by script-assisted edit-->

== External links == * [https://web.archive.org/web/20091026171102/http://1-core.com/library/digital/soft-cpu-cores/ Soft CPU Cores for FPGA] * [https://web.archive.org/web/20070615082550/http://www.ews.uiuc.edu/~pdabrows/soft_processor_comparison.html Detailed Comparison of 12 Soft Microprocessors] * [http://www.fpgacpu.org FPGA CPU News] * [http://f-cpu.org Freedom CPU website] * [http://opencores.org/projects Microprocessor cores] on Opencores.org (Expand the "Processor" tab) * [http://www.niktech.com NikTech] 32 bit RISC Microprocessor MANIK.

{{Soft microprocessors}} {{Programmable Logic}} {{DEFAULTSORT:Soft Microprocessor}} *