{{short description|Form of computer data storage}} {{Redirect|RAM|other uses|RAM (disambiguation)}} {{Distinguish|Random Access Memories|Random-access machine}} {{Use dmy dates|date=August 2025}} {{pp-protected|small=yes}}
[[File:Swissbit 2GB PC2-5300U-555.jpg|right|thumb|Example of writable volatile random-access memory: Synchronous dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers.]] {{Memory types}} [[File:Electronic Memory.jpg|thumb| A 64 bit memory chip die, the SP95 Phase 2 buffer memory produced at IBM mid-1960s, versus memory core iron rings]] [[File:Random Access Memory HyperX.jpg|thumb|8GB DDR3 RAM stick with a white heatsink]]
'''Random-access memory''' ('''RAM'''; {{IPAc-en|r|æ|m}}) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.<ref>{{cite web |title=RAM |url=https://dictionary.cambridge.org/dictionary/english/ram |website=Cambridge English Dictionary |access-date=11 July 2019 |archive-date=8 March 2021 |archive-url=https://web.archive.org/web/20210308202517/https://dictionary.cambridge.org/dictionary/english/ram |url-status=live }}</ref><ref>{{cite web |title=RAM |url=https://www.oxfordlearnersdictionaries.com/definition/american_english/ram_2 |website=Oxford Advanced Learner's Dictionary |access-date=11 July 2019 |archive-date=11 February 2021 |archive-url=https://web.archive.org/web/20210211031348/https://www.oxfordlearnersdictionaries.com/definition/american_english/ram_2 |url-status=live }}</ref> A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks and magnetic tape), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
In modern technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal–oxide–semiconductor) memory cells. RAM is normally associated with volatile types of memory where stored information is lost if power is removed. The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM).
Non-volatile RAM has also been developed<ref>{{cite magazine|last=Gallagher|first=Sean|title=Memory that never forgets: non-volatile DIMMs hit the market|url=https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|magazine=Ars Technica|url-status=live|archive-url=https://web.archive.org/web/20170708073138/https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|archive-date=July 8, 2017|date=April 4, 2013}}</ref> and other types of non-volatile memories allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of ROM and NOR flash memory.
The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their System/360 Model 95 computer, and Toshiba used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 electronic calculator, both based on bipolar transistors. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum |access-date=4 July 2019 |archive-date=3 October 2019 |archive-url=https://web.archive.org/web/20191003072028/https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |url-status=live }}</ref> In 1966, Dr. Robert Dennard invented modern DRAM architecture in which there's a single MOS transistor per capacitor.<ref>{{Cite patent|number=US3387286A|title=Field-effect transistor memory|gdate=1968-06-04|invent1=Dennard|inventor1-first=Robert H.|url=https://patents.google.com/patent/US3387286A}}</ref> The first commercial DRAM IC chip, the 1K Intel 1103, was introduced in October 1970. Synchronous dynamic random-access memory (SDRAM) was reintroduced with the Samsung KM48SL2000 chip in 1992.
==History== [[File:Early SSA accounting operations.jpg|thumb|These IBM tabulating machines from the mid-1930s used mechanical counters to store information.]]
Early computers used relays, mechanical counters<ref>{{cite web|url=http://www-03.ibm.com/ibm/history/reference/faq_0000000011.html|title=IBM Archives -- FAQ's for Products and Services|work=ibm.com|url-status=dead|archive-url=https://web.archive.org/web/20121023184527/http://www-03.ibm.com/ibm/history/reference/faq_0000000011.html|archive-date=2012-10-23}}</ref> or delay lines for main memory functions. Ultrasonic delay lines were serial devices which could only reproduce data in the order it was written. Drum memory could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of triode vacuum tubes, and later, out of discrete transistors, were used for smaller and faster memories such as registers. Such registers were relatively large and too costly to use for large amounts of data; generally, only a few dozen or few hundred bits of such memory could be provided.
The first practical form of random-access memory was the Williams tube. It stored data as electrically charged spots on the face of a cathode-ray tube. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the Manchester Baby computer, which first successfully ran a program on 21 June, 1948.<ref>{{Citation | last = Napper | first = Brian | title = Computer 50: The University of Manchester Celebrates the Birth of the Modern Computer | url = http://www.computer50.org/ | access-date = 26 May 2012 | url-status = dead | archive-url = https://web.archive.org/web/20120504133240/http://www.computer50.org/ | archive-date = 4 May 2012 }}</ref> In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.<ref>{{Citation |last1=Williams |first1=F. C. |last2=Kilburn |first2=T. |title=Electronic Digital Computers |journal=Nature |volume=162 |pages=487 |date=Sep 1948 |doi=10.1038/162487a0 |issue=4117 |postscript=. |bibcode=1948Natur.162..487W |s2cid=4110351|doi-access=free }} Reprinted in ''The Origins of Digital Computers''.</ref><ref>{{Citation |last1=Williams |first1=F. C. |last2=Kilburn |first2=T. |last3=Tootill |first3=G. C. |title=Universal High-Speed Digital Computers: A Small-Scale Experimental Machine |url=http://www.computer50.org/kgill/mark1/ssem.html |journal=Proc. IEE |date=Feb 1951 |volume=98 |issue=61 |pages=13–28 |postscript=. |doi=10.1049/pi-2.1951.0004 |url-status=dead |archive-url=https://web.archive.org/web/20131117101730/http://www.computer50.org/kgill/mark1/ssem.html |archive-date=2013-11-17|url-access=subscription }}</ref>
Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of computer memory until displaced by semiconductor memory in integrated circuits (ICs) during the early 1970s.<ref name="computerhistory1970"/>
Prior to the development of integrated read-only memory (ROM) circuits, ''permanent'' (or ''read-only'') random-access memory was often constructed using diode matrices driven by address decoders, or specially wound core rope memory planes.{{Citation needed|date=December 2016}}
Semiconductor memory appeared in the 1960s with bipolar memory, which used bipolar transistors. Although it was faster, it could not compete with the lower price of magnetic core memory.<ref name="computerhistory1966"/>
===MOS RAM=== In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650 |url-access=subscription |archive-date=23 December 2024 |access-date=8 September 2024 |archive-url=https://web.archive.org/web/20241223093624/https://iopscience.iop.org/article/10.1149/1.2428650 |url-status=live }}</ref> Subsequently, in 1960, a team demonstrated a working MOSFET at Bell Labs.<ref>{{Cite journal |last=KAHNG |first=D. |orig-date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |date=1991 |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5|url-access=subscription}}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> This led to the development of metal–oxide–semiconductor (MOS) memory by John Schmidt at Fairchild Semiconductor in 1964.<ref name="computerhistory1970" /><ref>{{Cite book |url=https://books.google.com/books?id=kG4rAQAAIAAJ&q=John+Schmidt |title=Solid State Design – Vol. 6 |date=1965 |publisher=Horizon House}}</ref> In addition to higher speeds, MOS semiconductor memory was cheaper and consumed less power than magnetic core memory.<ref name="computerhistory1970"/> The development of silicon-gate MOS integrated circuit (MOS IC) technology by Federico Faggin at Fairchild in 1968 enabled the production of MOS memory chips.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=Computer History Museum |access-date=10 August 2019 |archive-date=29 July 2020 |archive-url=https://web.archive.org/web/20200729145834/https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |url-status=live }}</ref> MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.<ref name="computerhistory1970" />
Integrated bipolar static random-access memory (SRAM) was invented by Robert H. Norman at Fairchild Semiconductor in 1963.<ref>{{cite patent | country = US | number = 3562721 | status = patent | title = Solid State Switching and Memory Apparatus | pubdate = 9 February 1971 | fdate = 5 March 1963 | pridate = 5 March 1963 | inventor = Robert H. Norman | invent1 = Fairchild Camera and Instrument Corporation }}</ref> It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964.<ref name="computerhistory1970"/> SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data.<ref name="ibm100">{{cite web |title=DRAM |url=https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram/ |website=IBM100 |publisher=IBM |access-date=20 September 2019 |date=9 August 2017 |archive-date=20 June 2019 |archive-url=https://web.archive.org/web/20190620014432/https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram/ |url-status=live }}</ref> Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the System/360 Model 95.<ref name="computerhistory1966"/>
Dynamic random-access memory (DRAM) allowed replacement of a 4- or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically refreshed every few milliseconds before the charge could leak away.
Toshiba's Toscal BC-1411 electronic calculator, which was introduced in 1965,<ref>[http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator Toscal BC-1411 calculator]. {{webarchive|url=https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator |date=2017-07-29}}, Science Museum, London.</ref><ref name="bc-spec"/><ref name="bc"/> used a form of capacitor bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors.<ref name="bc-spec"/><ref name="bc"/> Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum |access-date=4 July 2019 |archive-date=3 October 2019 |archive-url=https://web.archive.org/web/20191003072028/https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |url-status=live }}</ref>
[[File:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|right|CMOS 1-megabit (Mbit) DRAM chip, one of the last models developed by VEB Carl Zeiss, in 1989]] In 1966, Robert Dennard, while examining the characteristics of MOS technology, found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, and the MOS transistor could control writing the charge to the capacitor. This led to his development of modern DRAM architecture for which there is a single MOS transistor per capacitor.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="ibm100" /><ref name="Robert Dennard"/> The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8{{nbsp}}μm MOS process with a capacity of 1{{nbsp}}kbit, and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=Who Invented the Intel 1103 DRAM Chip? |access-date=2025-03-03 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead}}</ref>
The earliest DRAMs were often synchronized with the CPU clock and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book |author=P. Darche |url=https://books.google.com/books?id=rLC9zQEACAAJ |title=Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer |year=2020 |isbn=9781786305633 |page=59| publisher=John Wiley & Sons}}</ref><ref>{{cite book |author1=B. Jacob |url=https://books.google.com/books?id=SrP3aWed-esC |title=Memory Systems: Cache, DRAM, Disk |author2=S. W. Ng |author3=D. T. Wang |publisher=Morgan Kaufmann |year=2008 |isbn=9780080553849 |page=324}}</ref> In 1992 Samsung released KM48SL2000, which had a capacity of 16{{nbsp}}Mbit.<ref name="electronic-design">{{cite journal |title=Electronic Design |journal=Electronic Design |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref><ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=Samsung |access-date=19 June 2019 |date=August 1992 |archive-date=20 June 2019 |archive-url=https://web.archive.org/web/20190620131939/https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |url-status=live }}</ref> The first commercial double data rate SDRAM was Samsung's 64{{nbsp}}Mbit DDR SDRAM, released in June 1998.<ref>{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=Samsung Electronics |publisher=Samsung |date=10 February 1999 |archive-date=24 June 2019 |archive-url=https://web.archive.org/web/20190624193356/https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |url-status=live }}</ref> GDDR (graphics DDR) is a form of SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mbit memory chip in 1998.<ref>{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=Samsung Electronics |publisher=Samsung |date=17 September 1998 |archive-date=24 June 2019 |archive-url=https://web.archive.org/web/20190624193939/https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |url-status=live }}</ref>
==Types== In general, the term ''RAM'' refers solely to solid-state memory devices, and more specifically the main memory in most computers. The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a memory cell, typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less static power than DRAM. In modern computers, SRAM is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair (typically a MOSFET and MOS capacitor, respectively),<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=Wiley |isbn=0-471-33372-7 |page=214 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf |archive-date=23 January 2023 |access-date=7 October 2019 |archive-url=https://web.archive.org/web/20230123184804/http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf |url-status=dead }}</ref> which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.
Both static and dynamic RAM are considered ''volatile'', as their state is lost when power is removed from the system. By contrast, read-only memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as EEPROM and NOR flash) share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment.
ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using parity bits or error correction codes.
==Memory cell== {{main|Memory cell (computing)}} The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information. The cell can be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.
In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it is complex, expensive and has low storage density.
A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a 1 or a 0 in the cell. However, the charge in this capacitor slowly leaks away and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM. {| style="text-align:center; margin: 1em auto 1em auto" |thumb|class=skin-invert-image|SRAM cell (6 transistors)||thumb|DRAM cell (1 transistor and one capacitor) |}
==Addressing== To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines <math>A_0, A_1,...A_n</math>, and for each combination of bits that may be applied to these lines, a set of memory cells are selected. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.
Usually, several memory cells share the same address. For example, a 4-bit-wide RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different; for a 32-bit microprocessor, eight 4-bit RAM chips would be needed.
Often, more addresses are needed than can be provided by a single device. In that case, multiple devices are used, with external multiplexors used to select the device assigned to a specific address range. RAM is often byte addressable, although word-addressable RAM also exists.<ref>{{cite book |url=https://books.google.com/books?id=QGPHAl9GE-IC&dq=size+of+a+memory+address&pg=PA321 |isbn=978-0-7637-3769-6 |title=The Essentials of Computer Organization and Architecture |date=2006 |publisher=Jones & Bartlett Learning}}</ref><ref>{{cite book |url=https://books.google.com/books?id=-vQCEAAAQBAJ |title=Foundations of Computer Technology |isbn=978-1-000-15371-2 |last1=Anderson |first1=Alexander John |date=25 October 2020 |publisher=CRC Press}}</ref>
==Memory hierarchy== {{main|Memory hierarchy}} Many computer systems have a memory hierarchy consisting of processor registers, on-die SRAM caches, external caches, DRAM, memory paging systems and virtual memory or swap space on a SSD or hard drive. This entire pool of memory may be referred to as RAM from a programming perspective. The overall goal of using a memory hierarchy is to obtain the fastest possible average access time while minimizing the total cost of the entire memory system.
==Other uses of RAM== [[File:Crucial 16GB DDR5 SODIMM Ram.jpg|thumb|A Crucial DDR5 16GB SO-DIMM stick of laptop RAM, roughly half the size of standard DIMM used in desktop computers]] In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways.
===Virtual memory=== {{main|Virtual memory}} Most modern operating systems employ a method, known as virtual memory, of extending RAM capacity. A portion of the computer's hard drive or SSD is set aside for a ''paging file'' or a ''scratch partition'', and the combination of physical RAM and the paging file forms the system's total memory. For example, if a computer has 2 GB of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it. When the system runs low on physical memory, it can swap portions of RAM to the paging file to make room for new data. When the previously swapped information is needed again, another swap is performed to read the information back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.
===RAM disk=== {{main|RAM drive}} Software can ''partition'' a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM drive. A RAM drive typically loses the stored data when the computer is shut down.{{efn|Contents can be retained if memory is arranged to have a standby battery source, or changes to the RAM drive are written out to a nonvolatile disk before power down, in which case, RAM drive contents are reloaded from disk upon RAM drive initialization.}}
===Shadow RAM=== Sometimes, the contents of a relatively slow ROM chip are copied to RAM to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called ''shadowing'', is fairly common in both computers and embedded systems.
As a common example, the BIOS in typical personal computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Free memory is reduced by the size of the shadowed ROMs. Depending on the system, this may not result in increased performance and may cause incompatibilities. For example, some hardware may be inaccessible to the operating system if shadow RAM is used. On some systems, the benefit may be hypothetical because the BIOS is not used after booting.<ref>{{cite web|url=http://hardwarehell.com/articles/shadowram.htm|title=Shadow Ram|access-date=2007-07-24|url-status=live|archive-url=https://web.archive.org/web/20061029162135/http://hardwarehell.com/articles/shadowram.htm|archive-date=2006-10-29}}</ref>
=== Virtual private networks === Some virtual private network services utilize RAM servers to keep all runtime state, including session metadata and cryptographic material, in volatile memory. This is intended to improve security relative to disk-backed designs.<ref>{{Cite journal |last1=Nyholm |first1=Hannah |last2=Monteith |first2=Kristine |last3=Lyles |first3=Seth |last4=Gallegos |first4=Micaela |last5=DeSantis |first5=Mark |last6=Donaldson |first6=John |last7=Taylor |first7=Claire |date=2022-07-20 |title=The Evolution of Volatile Memory Forensics |journal=Journal of Cybersecurity and Privacy |language=en |volume=2 |issue=3 |pages=556–572 |doi=10.3390/jcp2030028 |doi-access=free |issn=2624-800X}}</ref><ref>{{Cite web |last1=Pudelko |first1=Maximilian |last2=Emmerich |first2=Paul |last3=Sebastian |first3=Sebastian |last4=Carle |first4=Georg |year=2020 |title=Performance Analysis of VPN Gateways |url=https://www.net.in.tum.de/fileadmin/bibtex/publications/papers/2020-ifip-moonwire.pdf |website=Technical University of Munich, Department of Informatics, Chair of Network Architectures and Services |access-date=25 September 2025 |archive-date=17 April 2024 |archive-url=https://web.archive.org/web/20240417174425/https://www.net.in.tum.de/fileadmin/bibtex/publications/papers/2020-ifip-moonwire.pdf |url-status=live }}</ref> In such a design, no data is written to hard drives; all information resides in volatile memory and is erased whenever the server is powered off or rebooted.<ref>{{Cite web |last=Castro |first=Chiara |date=2022-05-20 |title=ExpressVPN TrustedServer - everything you need to know |url=https://www.techradar.com/vpn/expressvpn-trustedserver-everything-you-need-to-know |access-date=2025-10-04 |website=TechRadar |language=en}}</ref>
==Memory wall== The '''memory wall''' is the growing disparity of speed between CPU and the response time of memory (known as memory latency) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 1986 to 2000, CPU speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.<ref>The term was coined in {{cite web |url=http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |title=Hitting the Memory Wall: Implications of the Obvious |access-date=2011-12-14 |url-status=live |archive-url=https://web.archive.org/web/20120406111104/http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |archive-date=2012-04-06}}.</ref>
Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 megabyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gigabytes with a response time of one clock cycle is difficult or impossible. Modern CPUs often still have 0 wait state cache memory, but, due to the bandwidth limitations of chip-to-chip communication, it must reside on the same chip as the CPU cores. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories.
CPU speed improvements slowed significantly, partly due to major physical barriers and partly because CPU designs have already hit the memory wall in some sense. Intel summarized these causes in a 2005 document.<ref>{{Cite web |title= Platform 2015: Intel Processor and Platform Evolution for the Next Decade |date= March 2, 2005 |url= http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |url-status= live |archive-url= https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |archive-date= April 27, 2011 }}</ref>
<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>
The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"<ref>{{Cite conference |first1=Vikas |last1=Agarwal |first2=M. S. |last2=Hrishikesh |first3=Stephen W. |last3=Keckler |first4=Doug |last4=Burger |title=Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures |url=http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf |conference=27th Annual International Symposium on Computer Architecture |conference-url=https://dl.acm.org/citation.cfm?id=339647 |book-title=Proceedings of the 27th Annual International Symposium on Computer Architecture |location=Vancouver, BC |date=June 10–14, 2000 |access-date=14 July 2018 |archive-date=5 November 2010 |archive-url=https://web.archive.org/web/20101105213832/http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf |url-status=live }}</ref> which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.
A different concept is the processor-memory performance gap, which can be addressed by 3D integrated circuits that reduce the distance between the control logic and memory cells that are further apart in a 2D chip.<ref>{{cite book |page=790 |url=https://books.google.com/books?id=1PgYS7zDCM8C&q=processor-memory+performance+gap&pg=PA790 |access-date=March 31, 2014 |title=Nanoelectronics and Information Technology |author=Rainer Waser |publisher=John Wiley & Sons |year=2012 |url-status=live |archive-url=https://web.archive.org/web/20160801114150/https://books.google.com/books?id=1PgYS7zDCM8C&pg=PA790&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CDYQ6AEwAg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn = 9783527409273|author-link = Rainer Waser}}</ref> Memory subsystem design requires a focus on the gap, which is widening over time.<ref>{{cite book |url=https://books.google.com/books?id=0IY7LW5J4JgC&q=processor-memory+performance+gap&pg=PA109 |page=109 |access-date=March 31, 2014 |title=Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings |author=Chris Jesshope and Colin Egan |publisher=Springer |date=2006 |url-status=live |archive-url=https://web.archive.org/web/20160801135254/https://books.google.com/books?id=0IY7LW5J4JgC&pg=PA109&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CEkQ6AEwBg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540400561 }}</ref> The main method of bridging the gap is the use of caches; small amounts of high-speed memory that houses data associated with recent operations near the processor, speeding up access to this data in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.<ref>{{cite book |url=https://books.google.com/books?id=7i9Z69lrYBoC&q=processor-memory+performance+gap&pg=PA90 |pages=90–91 |access-date=March 31, 2014 |title=Multiprocessor Systems-on-chips |author=Ahmed Amine Jerraya and Wayne Wolf |publisher=Morgan Kaufmann |year=2005 |url-status=live |archive-url=https://web.archive.org/web/20160801105357/https://books.google.com/books?id=7i9Z69lrYBoC&pg=PA90&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CFMQ6AEwCA#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9780123852519 }}</ref> There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.<ref>{{cite book |url=https://books.google.com/books?id=f0pJYJQMlmoC&q=processor-memory+performance+gap&pg=PA529 |page=529 |access-date=March 31, 2014 |title=Experimental and Efficient Algorithms: Third International Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3 |author=Celso C. Ribeiro and Simone L. Martins |publisher=Springer |year=2004 |url-status=live |archive-url=https://web.archive.org/web/20160801092734/https://books.google.com/books?id=f0pJYJQMlmoC&pg=PA529&dq=processor-memory+performance+gap&hl=en&sa=X&ei=1eM5U7veEaTx2QXM2oDYCw&ved=0CCwQ6AEwADgU#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540220671 }}</ref><!--User:Kvng/RTH-->
Solid-state hard drives have continued to increase in speed, from ~400 Mbit/s via SATA3 in 2012 up to ~7 GB/s via NVMe/PCIe in 2024, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane DDR5 8000MHz capable of 128 GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in server farms - 1 terabyte of SSD storage can be had for $200, while 1 TB of RAM would cost thousands of dollars.<ref>{{Cite web|url=https://www.minitool.com/news/ssd-prices-fall.html|title=SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!|date=2018-09-03|website=MiniTool|language=en-us|access-date=2019-03-28|archive-date=28 March 2019|archive-url=https://web.archive.org/web/20190328161357/https://www.minitool.com/news/ssd-prices-fall.html|url-status=live}}</ref><ref>{{Cite web|url=https://www.digitaltrends.com/computing/ram-prices-are-increasing-until-third-quarter-2017/|title=If you're buying or upgrading your PC, expect to pay more for RAM|last=Coppock|first=Mark|date=31 January 2017|website=www.digitaltrends.com|access-date=2019-03-28|archive-date=28 March 2019|archive-url=https://web.archive.org/web/20190328161357/https://www.digitaltrends.com/computing/ram-prices-are-increasing-until-third-quarter-2017/|url-status=live}}</ref>
==Timeline== {{See also|Flash memory#Timeline|Read-only memory#Timeline|Transistor count#Memory}}
===SRAM=== {| class="wikitable sortable" style="text-align:center" |+ Static random-access memory (SRAM) |- ! Date of introduction ! Chip name ! Capacity (bits) ! Access time ! SRAM type ! Manufacturer(s) ! data-sort-type="number" |Process ! MOSFET ! {{Abbr|Ref|Reference(s)}} |- |{{dts|1963|3}} |{{n/a}} |1 |{{?}} |Bipolar (cell) |Fairchild |{{n/a}} |{{n/a}} | rowspan="2" |<ref name="computerhistory1966">{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum |access-date=19 June 2019 |archive-date=3 October 2019 |archive-url=https://web.archive.org/web/20191003072028/https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |url-status=live }}</ref> |- | rowspan="3" |1965 |{{?}} |8 |{{?}} |Bipolar |IBM |{{?}} |{{n/a}} |- |SP95 |16 |{{?}} |Bipolar |IBM |{{?}} |{{n/a}} |<ref>{{cite book |title=IBM first in IC memory |url=https://www.computerhistory.org/collections/catalog/102770626 |via=Computer History Museum |year=1965 |publisher=IBM Corporation |access-date=19 June 2019 |archive-date=20 June 2019 |archive-url=https://web.archive.org/web/20190620174655/https://www.computerhistory.org/collections/catalog/102770626 |url-status=live }}</ref> |- |{{?}} |64 |{{?}} |MOSFET |Fairchild |{{?}} |PMOS |<ref name="Sah1303">{{cite journal |last=Sah |first=Chih-Tang |author-link=Chih-Tang Sah |title=Evolution of the MOS transistor-from conception to VLSI |journal=Proceedings of the IEEE |date=October 1988 |volume=76 |issue=10 |pages=1280–1326 (1303) |doi=10.1109/5.16328 |url=http://www.dejazzer.com/ece723/resources/Evolution_of_the_MOS_transistor.pdf |issn=0018-9219 |bibcode=1988IEEEP..76.1280S |archive-date=26 July 2020 |access-date=1 October 2019 |archive-url=https://web.archive.org/web/20200726192741/http://www.dejazzer.com/ece723/resources/Evolution_of_the_MOS_transistor.pdf |url-status=live }}</ref> |- | rowspan="2" |1966 |TMC3162 |16 |{{?}} |Bipolar (TTL) |Transitron |{{?}} |{{n/a}} |<ref name="computerhistory1970"/> |- |{{?}} |{{?}} |{{?}} |MOSFET |NEC |{{?}} |{{?}} |<ref name="shmj-mos"/> |- |rowspan="3" | 1968 |rowspan="3" | {{?}} |64 |{{?}} |MOSFET |Fairchild |{{?}} |PMOS |rowspan="2" | <ref name="shmj-mos"/> |- |144 |{{?}} |MOSFET |NEC |{{?}} |NMOS |- |512 |{{?}} |MOSFET |IBM |{{?}} |NMOS |<ref name="Sah1303"/> |- | rowspan="2" |1969 |{{?}} |128 |{{?}} |Bipolar |IBM |{{?}} |{{n/a}} |<ref name="computerhistory1966"/> |- |1101 |256 |850 ns |MOSFET |Intel |12,000 nm |PMOS |<ref name="Intel-Product-Timeline"/><ref name="shmj-1970s-sram">{{cite web |title=1970s: SRAM evolution |url=http://www.shmj.or.jp/english/pdf/ic/exhibi724E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019 |archive-date=27 June 2019 |archive-url=https://web.archive.org/web/20190627175824/http://www.shmj.or.jp/english/pdf/ic/exhibi724E.pdf |url-status=live }}</ref><ref name="Pimbley">{{cite book |last1=Pimbley |first1=J. |title=Advanced CMOS Process Technology |date=2012 |publisher=Elsevier |isbn=9780323156806 |page=7 |url=https://books.google.com/books?id=8EUWHSqevQoC&pg=PA7}}</ref><ref>{{Cite web|url=https://www.intel-vintage.info/intelmemory.htm|title=Intel Memory|website=Intel Vintage|access-date=2019-07-06|ref=intel-memory|archive-date=2022-03-19|archive-url=https://web.archive.org/web/20220319073833/https://www.intel-vintage.info/intelmemory.htm|url-status=usurped}}</ref> |- |1972 |2102 |1 kbit |{{?}} |MOSFET |Intel |{{?}} |NMOS |<ref name="Intel-Product-Timeline"/> |- | rowspan="2" |1974 |5101 |1 kbit |800 ns |MOSFET |Intel |{{?}} |CMOS |<ref name="Intel-Product-Timeline"/><ref name="Intel-1978-3">{{cite book |title=Component Data Catalog |date=1978 |publisher=Intel |page=3 |url=http://bitsavers.trailing-edge.com/components/intel/_dataBooks/1978_Intel_Component_Data_Catalog.pdf |access-date=27 June 2019 |archive-date=27 June 2019 |archive-url=https://web.archive.org/web/20190627175826/http://bitsavers.trailing-edge.com/components/intel/_dataBooks/1978_Intel_Component_Data_Catalog.pdf |url-status=live }}</ref> |- |2102A |1 kbit |350 ns |MOSFET |Intel |{{?}} |NMOS (depletion) |<ref name="Intel-Product-Timeline"/><ref>{{cite web |title=Silicon Gate MOS 2102A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |publisher=Intel |access-date=27 June 2019 |archive-date=10 September 2021 |archive-url=https://web.archive.org/web/20210910020543/https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |url-status=live }}</ref> |- |1975 |2114 |4 kbit |450 ns |MOSFET |Intel |{{?}} |NMOS |<ref name="Intel-Product-Timeline"/><ref name="Intel-1978-3"/> |- | rowspan="2" |1976 |2115 |1 kbit |70 ns |MOSFET |Intel |{{?}} |NMOS (HMOS) |<ref name="Intel-Product-Timeline"/><ref name="shmj-1970s-sram"/> |- |2147 |4 kbit |55 ns |MOSFET |Intel |{{?}} |NMOS (HMOS) |<ref name="Intel-Product-Timeline"/><ref name="hitachi-cmos">{{cite web |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019 |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705234921/http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |url-status=live }}</ref> |- |1977 |{{?}} |4 kbit |{{?}} |MOSFET |Toshiba |{{?}} |CMOS |<ref name="shmj-1970s-sram"/> |- | rowspan="2" |1978 |HM6147 |4 kbit |55 ns |MOSFET |Hitachi |3,000 nm |CMOS (twin-well) |<ref name="hitachi-cmos"/> |- |TMS4016 |16 kbit |{{?}} |MOSFET |Texas Instruments |{{?}} |NMOS |<ref name="shmj-1970s-sram"/> |- |rowspan="2" | 1980 |rowspan="2" | {{?}} |16 kbit |{{?}} |MOSFET |Hitachi, Toshiba |rowspan="2" | {{?}} |rowspan="2" | CMOS |rowspan="2" | <ref name="stl"/> |- |64 kbit |{{?}} |MOSFET |Matsushita |- |1981 |{{?}} |16 kbit |{{?}} |MOSFET |Texas Instruments |2,500 nm |NMOS |<ref name="stl"/> |- |{{dts|1981|10}} |{{?}} |4 kbit |18 ns |MOSFET |Matsushita, Toshiba |2,000 nm |CMOS |<ref>{{cite journal |last1=Isobe |first1=Mitsuo |last2=Uchida |first2=Yukimasa |last3=Maeguchi |first3=Kenji |last4=Mochizuki |first4=T. |last5=Kimura |first5=M. |last6=Hatano |first6=H. |last7=Mizutani |first7=Y. |last8=Tango |first8=H. |title=An 18 ns CMOS/SOS 4K static RAM |journal=IEEE Journal of Solid-State Circuits |date=October 1981 |volume=16 |issue=5 |pages=460–465 |doi=10.1109/JSSC.1981.1051623|bibcode=1981IJSSC..16..460I |s2cid=12992820 }}</ref> |- |1982 |{{?}} |64 kbit |{{?}} |MOSFET |Intel |1,500 nm |NMOS (HMOS) |<ref name="stl"/> |- |{{dts|1983|2}} |{{?}} |64 kbit |50 ns |MOSFET |Mitsubishi |{{?}} |CMOS |<ref>{{cite book |last1=Yoshimoto |first1=M. |last2=Anami |first2=K. |last3=Shinohara |first3=H. |last4=Yoshihara |first4=T. |last5=Takagi |first5=H. |last6=Nagao |first6=S. |last7=Kayano |first7=S. |last8=Nakano |first8=T. |title=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |chapter=A 64Kb full CMOS RAM with divided word line structure |date=1983 |volume=XXVI |pages=58–59 |doi=10.1109/ISSCC.1983.1156503|s2cid=34837669 }}</ref> |- |1984 |{{?}} |256 kbit |{{?}} |MOSFET |Toshiba |1,200 nm |CMOS |<ref name="stl"/><ref name="Pimbley"/> |- |1987 |{{?}} |1 Mbit |{{?}} |MOSFET |Sony, Hitachi, Mitsubishi, Toshiba |{{?}} |CMOS |<ref name="stl"/> |- |{{dts|1987|12}} |{{?}} |256 kbit |10 ns |BiMOS |Texas Instruments |800 nm |BiCMOS |<ref>{{cite book |last1=Havemann |first1=Robert H. |last2=Eklund |first2=R. E. |last3=Tran |first3=Hiep V. |last4=Haken |first4=R. A. |last5=Scott |first5=D. B. |last6=Fung |first6=P. K. |last7=Ham |first7=T. E. |last8=Favreau |first8=D. P. |last9=Virkus |first9=R. L. |title=1987 International Electron Devices Meeting |chapter=An 0.8 μm 256K BiCMOS SRAM technology |date=December 1987 |pages=841–843 |doi=10.1109/IEDM.1987.191564|s2cid=40375699 }}</ref> |- |1990 |{{?}} |4 Mbit |15{{ndash}}23 ns |MOSFET |NEC, Toshiba, Hitachi, Mitsubishi |{{?}} |rowspan="2" | CMOS |rowspan="2" | <ref name="stl"/> |- |1992 |{{?}} |16 Mbit |12{{ndash}}15 ns |MOSFET |Fujitsu, NEC |400 nm |- |{{dts|1994|12}} |{{?}} |512 kbit |2.5 ns |MOSFET |IBM |{{?}} |CMOS (SOI) |<ref>{{cite journal |last1=Shahidi |first1=Ghavam G. |author1-link=Ghavam Shahidi |last2=Davari |first2=Bijan |author2-link=Bijan Davari |last3=Dennard |first3=Robert H. |author3-link=Robert H. Dennard |last4=Anderson |first4=C. A. |last5=Chappell |first5=B. A. |last6=Chappell |first6=T. I. |last7=Comfort |first7=J. H. |last8=Franch |first8=R. L. |last9=McFarland |first9=P. A. |last10=Neely |first10=J. S. |last11=Ning |first11=T. H. |last12=Polcari |first12=M. R. |last13=Warnock |first13=J. D. |display-authors=5 |title=A room temperature 0.1 μm CMOS on SOI |journal=IEEE Transactions on Electron Devices |date=December 1994 |volume=41 |issue=12 |pages=2405–2412 |doi=10.1109/16.337456|bibcode=1994ITED...41.2405S |s2cid=108832941 }}</ref> |- | rowspan="2" |1995 | rowspan="2" |{{?}} |4 Mbit |6 ns |Cache (SyncBurst) |Hitachi |100 nm |CMOS |<ref name="smithsonian-japan"/> |- |256 Mbit |{{?}} |MOSFET |Hyundai |{{?}} |CMOS |<ref name="hynix90s-skhynix.com">{{cite web |title=History: 1990s |url=https://www.skhynix.com/eng/about/history1990.jsp |website=SK Hynix |access-date=6 July 2019 |archive-date=5 February 2021 |archive-url=https://web.archive.org/web/20210205032928/https://www.skhynix.com/eng/about/history1990.jsp |url-status=dead }}</ref> |}
===DRAM=== {| class="wikitable sortable" style="text-align:center" |+ Dynamic random-access memory (DRAM) |- ! Date of introduction ! Chip name ! Capacity (bits) ! DRAM type ! Manufacturer(s) ! data-sort-type="number" |Process !MOSFET ! data-sort-type="number" | Area ! {{Abbr|Ref|Reference(s)}} |- |1965 |{{n/a}} |1 bit |DRAM (cell) |Toshiba |{{n/a}} |{{n/a}} |{{n/a}} |<ref name="bc-spec">{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Spec Sheet for Toshiba "TOSCAL" BC-1411|website=Old Calculator Web Museum|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref name="bc">[http://www.oldcalculatormuseum.com/toshbc1411.html Toshiba "Toscal" BC-1411 Desktop Calculator] {{webarchive|url=https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html |date=2007-05-20 }}</ref> |- |1967 |{{n/a}} |1 bit |DRAM (cell) |IBM |{{n/a}} |MOS |{{n/a}} |<ref name="Robert Dennard">{{cite web |title=Robert Dennard |url=https://www.britannica.com/biography/Robert-Dennard |website=Encyclopedia Britannica |access-date=8 July 2019 |archive-date=26 October 2020 |archive-url=https://web.archive.org/web/20201026192558/https://www.britannica.com/biography/Robert-Dennard |url-status=live }}</ref><ref name="shmj-mos">{{cite web |title=Late 1960s: Beginnings of MOS memory |url=http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf |website=Semiconductor History Museum of Japan |date=2019-01-23 |access-date=27 June 2019 |archive-date=27 June 2019 |archive-url=https://web.archive.org/web/20190627052600/http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf |url-status=live }}</ref> |- |1968 |{{?}} |256 bit |DRAM (IC) |Fairchild |{{?}} |PMOS |{{?}} |<ref name="computerhistory1970">{{cite web |title=1970: Semiconductors compete with magnetic cores |url=https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/ |website=Computer History Museum |access-date=19 June 2019 |archive-date=3 October 2019 |archive-url=https://web.archive.org/web/20191003063436/https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/ |url-status=live }}</ref> |- |1969 |{{n/a}} |1 bit |DRAM (cell) |Intel |{{n/a}} |PMOS |{{n/a}} |<ref name="shmj-mos"/> |- | rowspan="2" |1970 |1102 |1 kbit |DRAM (IC) |Intel, Honeywell |{{?}} |PMOS |{{?}} |<ref name="shmj-mos"/> |- |1103 |1 kbit |DRAM |Intel |8,000 nm |PMOS |10 mm<sup>2</sup> |<ref name="Intel2003">{{cite web |title=Intel: 35 Years of Innovation (1968–2003) |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf |publisher=Intel |year=2003 |access-date=26 June 2019 |archive-date=4 November 2021 |archive-url=https://web.archive.org/web/20211104070452/https://www.intel.com/Assets/PDF/General/35yrs.pdf |url-status=live }}</ref><ref name="HC">[http://history-computer.com/ModernComputer/Basis/dram.html ''The DRAM memory of Robert Dennard''] {{Webarchive|url=https://web.archive.org/web/20200801004808/https://history-computer.com/ModernComputer/Basis/dram.html |date=2020-08-01 }} history-computer.com</ref><ref name="Lojek-1103">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=9783540342588 |pages=362–363 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA362 |quote=The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm<sup>2</sup> memory cell size, a die size just under 10 mm<sup>2</sup>, and sold for around $21.}}</ref> |- | rowspan="2" |1971 |μPD403 |1 kbit |DRAM |NEC |{{?}} |NMOS |{{?}} |<ref>{{cite web |title=Manufacturers in Japan enter the DRAM market and integration densities are improved |url=http://www.shmj.or.jp/english/pdf/ic/exhibi745E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019 |archive-date=27 June 2019 |archive-url=https://web.archive.org/web/20190627161053/http://www.shmj.or.jp/english/pdf/ic/exhibi745E.pdf |url-status=live }}</ref> |- |{{?}} |2 kbit |DRAM |General Instrument |{{?}} |PMOS |13 mm<sup>2</sup> |<ref name="Gealow">{{cite web |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=Massachusetts Institute of Technology |via=CORE |date=10 August 1990 |pages=149–166 |access-date=25 June 2019 |archive-date=25 June 2019 |archive-url=https://web.archive.org/web/20190625023333/https://core.ac.uk/download/pdf/4426308.pdf |url-status=live }}</ref> |- |1972 |2107 |4 kbit |DRAM |Intel |{{?}} |NMOS |{{?}} |<ref name="Intel-Product-Timeline">{{cite web|url=http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|title=A chronological list of Intel products. The products are sorted by date.|date=July 2005|work=Intel museum|publisher=Intel Corporation|archive-url=https://web.archive.org/web/20070809053720/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|archive-date=August 9, 2007|access-date=July 31, 2007}}</ref><ref>{{cite web |title=Silicon Gate MOS 2107A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMDJjOGZkNzUtNzMxMS00ZWM5LWIzNjEtZTg1MDZiNjM3ZDBm/view |publisher=Intel |access-date=27 June 2019}}</ref> |- |1973 |{{?}} |8 kbit |DRAM |IBM |{{?}} |PMOS |19 mm<sup>2</sup> |<ref name="Gealow"/> |- |1975 |2116 |16 kbit |DRAM |Intel |{{?}} |NMOS |{{?}} |<ref>{{cite web |title=One of the Most Successful 16K Dynamic RAMs: The 4116 |url=http://smithsonianchips.si.edu/augarten/p50.htm |url-status=dead |website=National Museum of American History |publisher=Smithsonian Institution |access-date=20 June 2019 |archive-url=https://web.archive.org/web/20230531180053/https://smithsonianchips.si.edu/augarten/p50.htm |archive-date=2023-05-31}}</ref><ref name="computerhistory1970"/> |- |1977 |{{?}} |64 kbit |DRAM |NTT |{{?}} |NMOS |35 mm<sup>2</sup> |<ref name="Gealow"/> |- | rowspan="2" |1979 |MK4816 |16 kbit |PSRAM |Mostek |{{?}} |NMOS |{{?}} |<ref>{{cite book |title=Memory Data Book And Designers Guide |date=March 1979 |publisher=Mostek |pages=9 & 183 |url=http://www.bitsavers.org/components/mostek/_dataBooks/1979_Mostek_Memory_Data_Book_and_Designers_Guide_Mar79.pdf |archive-date=27 September 2019 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190927110203/http://bitsavers.org/components/mostek/_dataBooks/1979_Mostek_Memory_Data_Book_and_Designers_Guide_Mar79.pdf |url-status=live }}</ref> |- |{{?}} |64 kbit |DRAM |Siemens |{{?}} |VMOS |25 mm<sup>2</sup> |<ref name="Gealow"/> |- |1980 |{{?}} |256 kbit |DRAM |NEC, NTT |1,000{{ndash}}1,500 nm |NMOS |34{{ndash}}42 mm<sup>2</sup> |<ref name="Gealow"/> |- |1981 |{{?}} |288 kbit |DRAM |IBM |{{?}} |MOS |25 mm<sup>2</sup> |<ref>{{cite web |title=The Cutting Edge of IC Technology: The First 294,912-Bit (288K) Dynamic RAM |url=http://smithsonianchips.si.edu/augarten/p66.htm |website=National Museum of American History |publisher=Smithsonian Institution |access-date=20 June 2019 |archive-date=14 December 2018 |archive-url=https://web.archive.org/web/20181214220547/http://smithsonianchips.si.edu/augarten/p66.htm |url-status=live }}</ref> |- |rowspan="2" | 1983 |rowspan="2" | {{?}} |64 kbit |DRAM |Intel |1,500 nm |CMOS |20 mm<sup>2</sup> |rowspan="2" | <ref name="Gealow"/> |- |256 kbit |DRAM |NTT |{{?}} |CMOS |31 mm<sup>2</sup> |- |{{sort|1984|January 5, 1984}} |{{?}} |8 Mbit |DRAM |Hitachi |{{?}} |MOS |{{?}} |<ref>{{cite web |title=Computer History for 1984 |url=https://www.computerhope.com/history/1984.htm |website=Computer Hope |access-date=25 June 2019 |archive-date=25 June 2019 |archive-url=https://web.archive.org/web/20190625023333/https://www.computerhope.com/history/1984.htm |url-status=live }}</ref><ref>{{cite journal |title=Japanese Technical Abstracts |journal=Japanese Technical Abstracts |date=1987 |volume=2 |issue=3–4 |page=161 |url=https://books.google.com/books?id=Fa0kAQAAIAAJ |publisher=University Microfilms |quote=The announcement of 1M DRAM in 1984 began the era of megabytes.}}</ref> |- | rowspan="2" |{{sort|1984|February 1984}} | rowspan="2" |{{?}} | rowspan="2" |1 Mbit | rowspan="2" |DRAM |Hitachi, NEC |1,000 nm |NMOS |74{{ndash}}76 mm<sup>2</sup> |<ref name="Gealow"/><ref name="Robinson">{{cite journal |last1=Robinson |first1=Arthur L. |title=Experimental Memory Chips Reach 1 Megabit: As they become larger, memories become an increasingly important part of the integrated circuit business, technologically and economically |journal=Science |date=11 May 1984 |volume=224 |issue=4649 |pages=590–592 |doi=10.1126/science.224.4649.590 |pmid=17838349 |issn=0036-8075}}</ref> |- |NTT |800 nm |CMOS |53 mm<sup>2</sup> |<ref name="Gealow"/><ref name="Robinson"/> |- |1984 |TMS4161 |64 kbit |DPRAM (VRAM) |Texas Instruments |{{?}} |NMOS |{{?}} |<ref name="ti1984">{{cite book |title=MOS Memory Data Book |url=http://bitsavers.trailing-edge.com/components/ti/_dataBooks/1984_TI_MOS_Memory_Data_Book.pdf |publisher=Texas Instruments |year=1984 |pages=4–15 |access-date=21 June 2019 |archive-date=21 June 2019 |archive-url=https://web.archive.org/web/20190621142626/http://bitsavers.trailing-edge.com/components/ti/_dataBooks/1984_TI_MOS_Memory_Data_Book.pdf |url-status=live }}</ref><ref>{{cite web |title=Famous Graphics Chips: TI TMS34010 and VRAM |url=https://www.computer.org/publications/tech-news/chasing-pixels/Famous-Graphics-Chips-IBMs-professional-graphics-the-PGC-and-8514A/Famous-Graphics-Chips-TI-TMS34010-and-VRAM |website=IEEE Computer Society |date=10 January 2019 |access-date=29 June 2019 |archive-date=22 June 2019 |archive-url=https://web.archive.org/web/20190622012912/https://www.computer.org/publications/tech-news/chasing-pixels/Famous-Graphics-Chips-IBMs-professional-graphics-the-PGC-and-8514A/Famous-Graphics-Chips-TI-TMS34010-and-VRAM |url-status=live }}</ref> |- |{{sort|1985|January 1985}} |μPD41264 |256 kbit |DPRAM (VRAM) |NEC |{{?}} |NMOS |{{?}} |<ref>{{cite web |title=μPD41264 256K Dual Port Graphics Buffer |url=https://console5.com/techwiki/images/4/4b/UPD41264.pdf |publisher=NEC Electronics |access-date=21 June 2019}}</ref><ref>{{cite web |title=Sense amplifier circuit for switching plural inputs at low power |url=https://patents.google.com/patent/US4808857 |website=Google Patents |access-date=21 June 2019 |archive-date=22 October 2019 |archive-url=https://web.archive.org/web/20191022092121/https://patents.google.com/patent/US4808857 |url-status=live }}</ref> |- |{{sort|1986|June 1986}} |{{?}} |1 Mbit |PSRAM |Toshiba |{{?}} |CMOS |{{?}} |<ref>{{cite journal |title=Fine CMOS techniques create 1M VSRAM |journal=Japanese Technical Abstracts |date=1987 |volume=2 |issue=3–4 |page=161 |url=https://books.google.com/books?id=Fa0kAQAAIAAJ |publisher=University Microfilms}}</ref> |- |rowspan="2" | 1986 |rowspan="2" | {{?}} |rowspan="2" | 4 Mbit |rowspan="2" | DRAM |NEC |800 nm |NMOS |99 mm<sup>2</sup> |rowspan="2" | <ref name="Gealow"/> |- |Texas Instruments, Toshiba |1,000 nm |CMOS |100{{ndash}}137 mm<sup>2</sup> |- |1987 |{{?}} |16 Mbit |DRAM |NTT |700 nm |CMOS |148 mm<sup>2</sup> |<ref name="Gealow"/> |- |{{sort|1987|October 1988}} |{{?}} |512 kbit |HSDRAM |IBM |1,000 nm |CMOS |78 mm<sup>2</sup> |<ref>{{cite journal |last1=Hanafi |first1=Hussein I. |last2=Lu |first2=Nicky C. C. |last3=Chao |first3=H. H. |last4=Hwang |first4=Wei |last5=Henkels |first5=W. H. |last6=Rajeevakumar |first6=T. V. |last7=Terman |first7=L. M. |last8=Franch |first8=Robert L. |title=A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate |journal=IEEE Journal of Solid-State Circuits |date=October 1988 |volume=23 |issue=5 |pages=1140–1149 |doi=10.1109/4.5936|bibcode=1988IJSSC..23.1140L }}</ref> |- |1991 |{{?}} |64 Mbit |DRAM |Matsushita, Mitsubishi, Fujitsu, Toshiba |400 nm |CMOS |{{?}} | rowspan="2" |<ref name="stl">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-date=2 November 2023|archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html|url-status=dead}}</ref> |- |1993 |{{?}} |256 Mbit |DRAM |Hitachi, NEC |250 nm |CMOS |{{?}} |- |1995 |{{?}} |4 Mbit |DPRAM (VRAM) |Hitachi |{{?}} |CMOS |{{?}} |<ref name="smithsonian-japan">{{cite web |title=Japanese Company Profiles |url=http://smithsonianchips.si.edu/ice/cd/PROF96/JAPAN.PDF |publisher=Smithsonian Institution |year=1996 |access-date=27 June 2019 |archive-date=19 April 2023 |archive-url=https://web.archive.org/web/20230419065056/http://smithsonianchips.si.edu/ice/cd/PROF96/JAPAN.PDF |url-status=live }}</ref> |- | rowspan="2" |{{sort|1995|January 9, 1995}} | rowspan="2" |{{?}} | rowspan="2" |1 Gbit | rowspan="2" |DRAM |NEC |250 nm |CMOS |{{?}} |rowspan="2" |<ref name="HB19950109">{{usurped|1=[https://web.archive.org/web/20140827092848/http://business.highbeam.com/3591/article-1G1-16482653/breaking-gigabit-barrier-drams-isscc-portend-major ''Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development)'']}}, January 9, 1995</ref><ref name="smithsonian-japan"/> |- |Hitachi |160 nm |CMOS |{{?}} |- |1996 |{{?}} |4 Mbit |FRAM |Samsung |{{?}} |NMOS |{{?}} |<ref>{{cite book |last1=Scott |first1=J.F. |chapter=Nano-Ferroelectrics |editor-last1=Tsakalakos |editor-first1=Thomas |editor-last2=Ovid'ko |editor-first2=Ilya A. |editor-last3=Vasudevan |editor-first3=Asuri K. |title=Nanostructures: Synthesis, Functional Properties and Application |date=2003 |publisher=Springer Science & Business Media |isbn=9789400710191 |pages=584–600 (597) |chapter-url=https://books.google.com/books?id=z2ryCAAAQBAJ&pg=PA597}}</ref> |- |1997 |{{?}} |4 Gbit |QLC |NEC |150 nm |CMOS |{{?}} |<ref name="stl"/> |- |1998 |{{?}} |4 Gbit |DRAM |Hyundai |{{?}} |CMOS |{{?}} |<ref name="hynix90s-skhynix.com"/> |- |{{sort|2001|February 2001}} |{{?}} |4 Gbit |DRAM |Samsung |100 nm |CMOS |{{?}} |<ref name="stl"/><ref>{{cite web |title=A Study of the DRAM industry |url=https://dspace.mit.edu/bitstream/handle/1721.1/59138/659514510-MIT.pdf |publisher=MIT |date=8 June 2010 |access-date=29 June 2019 |archive-date=29 June 2019 |archive-url=https://web.archive.org/web/20190629232100/https://dspace.mit.edu/bitstream/handle/1721.1/59138/659514510-MIT.pdf |url-status=live }}</ref> |- |{{sort|2001|June 2001}} |TC51W3216XB |32 Mbit |PSRAM |Toshiba |{{?}} |CMOS |{{?}} |<ref>{{cite news |title=Toshiba's new 32 Mb Pseudo-SRAM is no fake |url=https://www.theengineer.co.uk/toshibas-new-32-mb-pseudo-sram-is-no-fake/ |access-date=29 June 2019 |work=The Engineer |date=24 June 2001 |language=en-UK |archive-date=29 June 2019 |archive-url=https://web.archive.org/web/20190629232051/https://www.theengineer.co.uk/toshibas-new-32-mb-pseudo-sram-is-no-fake/ |url-status=dead }}</ref> |}
===SDRAM=== {{Transcluded section|Synchronous dynamic random-access memory|part=yes}} {{trim|{{#section::Synchronous dynamic random-access memory|SDRAM timeline}} }}
==Notes== {{Notelist}}
==See also== {{Columns-list|colwidth=30em| * CAS latency (CL) * Chip creep * Electrochemical RAM * Hybrid Memory Cube * List of RAM chip manufacturers * List of RAM module manufacturers * Memory geometry * Memory module * Multi-channel memory architecture * RAM parity * Read-mostly memory (RMM) * Regenerative capacitor memory * Registered/buffered memory }}
{{Portal|Technology}}
==References== {{reflist}}
==External links== * {{Commons-inline|RAM}}
{{Basic computer components}}
{{Authority control}}
{{DEFAULTSORT:Random-Access Memory}} Category:American inventions Category:Computer architecture Category:Computer memory Category:Random-access memory