Noise margin

{{More citations needed|date=November 2008}} In electrical engineering, '''Noise margin''' is the maximum voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level.<ref>{{Cite web|url=https://www.jedec.org/standards-documents/dictionary/terms/noise-margin|title=noise margin {{!}} JEDEC|website=www.jedec.org|access-date=2019-03-01}}</ref> It is commonly used in at least two contexts as follows:

*In telecommunications engineering, noise margin is the ratio by which the signal exceeds the minimum acceptable amount. It is normally measured in decibels. *In a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper '0' (logic low) or '1' (logic high). For example, a digital circuit might be designed to swing between 0.0 and 1.2 volts, with anything below 0.2 volts considered a '0', and anything above 1.0 volts considered a '1'. Then the noise margin for a '0' would be the amount that a signal is below 0.2 volts, and the noise margin for a '1' would be the amount by which a signal exceeds 1.0 volt. In this case noise margins are measured as an absolute voltage, not a ratio. Noise margins for CMOS chips are usually much greater than those for TTL because the V_{OH min} is closer to the power supply voltage and V_{OL max} is closer to zero. **Real digital inverters do not instantaneously switch from a logic high (1) to a logic low (0), there is some capacitance. While an inverter is transitioning from a logic high to low, there is an undefined region where the voltage cannot be considered high or low. This is considered a noise margin. There are two noise margins to consider: Noise margin high (N_MH) and noise margin low (N_ML). N_MH is the amount of voltage between an inverter transitioning from a logic high (1) to a logic low (0) and vice versa for N_ML. The equations are as follows: N_MH ≡ V_OH - V_IH and N_ML ≡ V_IL - V_OL.<ref>{{Cite web|url=http://web.mit.edu/6.012/www/SP07-L11.pdf|title=MIT PowerPoint}}</ref> Typically, in a CMOS inverter V_OH will equal V_DD and V_OL will equal the ground potential, as mentioned above. ***V_IH is defined as the highest input voltage at which the slope of the voltage transfer characteristic (VTC) is equal to -1,<ref name=":0">{{Cite book|url=https://archive.org/details/introductiontodi00gopa|title=Introduction to digital electronic circuits|last=Gopal.|first=Gopalan, K.|date=1996|publisher=Irwin|isbn=0256120897|location=Chicago|oclc=33664747|url-access=registration}}</ref> where the VTC is the plot of all valid output voltages vs. input voltages. Similarly, V_IL is defined as the lowest input voltage where slope of the VTC is equal to -1.

In practice, noise margins are the amount of noise, that a logic circuit can withstand. Noise margins are generally defined so that positive values ensure proper operation, and negative margins result in compromised operation, or outright failure.<ref name=":0" />

== See also == * Circuit * Signal integrity * Substrate coupling * G.992.1 * Signal-to-noise ratio * Signal

== References == <references />

== External links == *[http://dmt.mhilfe.de/ DMT], a DSL monitoring and downstream noise margin tweaking program. *[http://web.mit.edu/6.012/www/SP07-L11.pdf MIT], PDF of a PowerPoint Presentation on for Digital Noise Margin.

Category:Electronic engineering Category:Electronic design Category:Electronic design automation Category:Integrated circuits