{{Short description|Low-level instructions used in some designs to implement complex machine instructions}} {{Use dmy dates|date=May 2020|cs1-dates=y}} [[File:Micro-operations.svg|thumb|right|upright=2.1|A high-level illustration showing the decomposition of machine instructions into micro-operations, performed during typical fetch-decode-execute cycles{{r|maine-coa|page=11}}]]
In computer central processing units, '''micro-operations''' (also known as '''micro-ops''' or '''μops''', historically also as '''micro-actions'''<ref name="Ferranti_1968"/>) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).<ref name="agner.org">{{cite web | url = http://www.agner.org/optimize/microarchitecture.pdf | title = The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers | date = 2014-02-19 | accessdate = 2014-03-21 | author = Agner Fog | website = agner.org |author-link=Agner Fog }}</ref>{{rp|8–9}}
Usually, micro-operations perform basic operations on data stored in one or more registers, including transferring data between registers or between registers and external buses of the central processing unit (CPU), and performing arithmetic or logical operations on registers. Micro-operations are usually represented using register transfer language.<ref>{{Cite web |work=Systems I: Computer Organization and Architecture |title=Lecture 9 - Register Transfer and Microoperations |url=https://home.adelphi.edu/~siegfried/cs371/371l9.pdf |page=2}}</ref> In a typical fetch-decode-execute cycle, each step of a macro-instruction is decomposed during its execution so the CPU determines and steps through a series of micro-operations. The execution of micro-operations is performed under control of the CPU's control unit, which decides on their execution while performing various optimizations such as reordering, fusion and caching.<ref name="maine-coa">{{cite web | url = http://umcs.maine.edu/~cmeadow/courses/cos335/COA15.pdf | title = Computer Organization and Architecture, Chapter 15. Control Unit Operation | date = 2010-03-16 | accessdate = 2014-12-29 | website = umcs.maine.edu }}</ref>
== {{Anchor|MICRO-FUSION|MACRO-FUSION}}Optimizations == Various forms of μops have long been the basis for traditional microcode routines used to simplify the implementation of a particular CPU design or perhaps just the sequencing of certain multi-step operations or addressing modes. More recently, μops have also been employed in a different way in order to let modern CISC processors more easily handle asynchronous parallel and speculative execution: As with traditional microcode, one or more table lookups (or equivalent) is done to locate the appropriate μop-sequence based on the encoding and semantics of the machine instruction (the decoding or translation step), however, instead of having rigid μop-sequences controlling the CPU directly from a microcode-ROM, μops are here dynamically buffered for rescheduling before being executed.<ref name="nehalem">{{cite web |url = http://sc.tamu.edu/systems/eos/nehalem.pdf |title = The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms |date = 2011-03-17 |accessdate = 2014-03-21 |author = Michael E. Thomadakis |publisher = Texas A&M University |url-status = dead |archiveurl = https://web.archive.org/web/20140811023120/http://sc.tamu.edu/systems/eos/nehalem.pdf |archivedate = 2014-08-11 }}</ref>{{rp|6–7, 9–11}}
This buffering means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or hard-wired) design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction-level parallelism out of a normal single-threaded program possible (provided that dependencies are checked, etc.). It opens up for more analysis and therefore also for reordering of code sequences in order to dynamically optimize mapping and scheduling of μops onto machine resources (such as ALUs, load/store units, etc.). As this happens on the μop-level, sub-operations of different machine (macro) instructions may often intermix in a particular μop-sequence, forming partially reordered machine instructions as a direct consequence of the out-of-order dispatching of microinstructions from several macro instructions. However, this is not the same as the ''micro-op fusion'', which aims at the fact that a more complex microinstruction may replace a few simpler microinstructions in certain cases, typically in order to minimize state changes and usage of the queue and re-order buffer space, therefore reducing power consumption. Micro-op fusion is used in some modern CPU designs.<ref name="agner.org" />{{rp|89–91, 105–106}}<ref name="nehalem" />{{rp|6–7, 9–15}}
Execution optimization has gone even further; processors not only translate many machine instructions into a series of μops, but also do the opposite when appropriate; they combine certain machine instruction sequences (such as a compare followed by a conditional jump) into a more complex μop which fits the execution model better and thus can be executed faster or with less machine resources involved. This is also known as ''macro-op fusion''.<ref name="agner.org" />{{rp|106–107}}<ref name="nehalem" />{{rp|12–13}}
Another way to try to improve performance is to cache the decoded micro-operations in a micro-operation cache, so that if the same macroinstruction is executed again, the processor can directly access the decoded micro-operations from the cache, instead of decoding them again. The execution trace cache found in Intel NetBurst microarchitecture (Pentium 4) is a widespread example of this technique.<ref>{{cite web | url = http://www.anandtech.com/show/661/5 | archive-url = https://web.archive.org/web/20100526025110/http://www.anandtech.com/show/661/5 | url-status = dead | archive-date = 26 May 2010 | title = Intel Pentium 4 1.4GHz & 1.5GHz | date = 2000-11-20 | accessdate = 2013-10-06 | publisher = AnandTech }}</ref> The size of this cache may be stated in terms of how many thousands (or strictly multiple of 1024) of micro-operations it can store: ''Kμops''.<ref>{{cite book | chapter-url = http://cecs.uci.edu/~papers/compendium94-03/papers/2001/islped01/pdffiles/p004.pdf | chapter = Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA | author1 = Baruch Solomon | author2 = Avi Mendelson | author3 = Doron Orenstein | author4 = Yoav Almog | author5 = Ronny Ronen | title = ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) | date = August 2001 | pages = 4–9 | accessdate = 2014-03-21 | publisher = Intel | doi = 10.1109/LPE.2001.945363 | isbn = 1-58113-371-5 | s2cid = 10934861 }}</ref>
== References == {{Reflist|refs= <ref name="Ferranti_1968">{{cite book |title=FM1600B Microcircuit Computer Ferranti Digital Systems |date=October 1968 |orig-year=September 1968 |publisher=Ferranti Limited, Digital Systems Department |location=Bracknell, Berkshire, UK |id=List DSD 68/6 |url=https://www.sba.unipi.it/sites/default/files/2015_05_29_08_44_13.pdf |access-date=2020-05-19 |url-status=live |archive-url=https://web.archive.org/web/20200519075443/https://www.sba.unipi.it/sites/default/files/2015_05_29_08_44_13.pdf |archive-date=2020-05-19}}</ref> }}
{{CPU technologies}}
Category:Instruction processing Category:Central processing unit