{{Short description|Insulator in semiconductor devices}} In semiconductor manufacturing, a '''low-κ''' is a material with a small relative dielectric constant (κ, kappa) relative to silicon dioxide. Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of microelectronic devices, colloquially referred to as extending Moore's law. In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds (in case of synchronous circuits) and lower heat dissipation. In conversation such materials may be referred to as "low-k" (spoken "low-kay") rather than "low-κ" (low-kappa).

==Low-κ materials== In integrated circuits, and CMOS devices, silicon dioxide can readily be formed on surfaces of Si through thermal oxidation, and can further be deposited on the surfaces of conductors using chemical vapor deposition or various other thin film fabrication methods. Due to the wide range of methods that can be used to cheaply form silicon dioxide layers, this material is used conventionally as the baseline to which other low permittivity dielectrics are compared. The relative dielectric constant of SiO<sub>2</sub>, the insulating material still used in silicon chips, is 3.9. This number is the ratio of the permittivity of SiO<sub>2</sub> divided by permittivity of vacuum, ε<sub>SiO<sub>2</sub></sub>/ε<sub>0</sub>, where ε<sub>0</sub> = 8.854×10<sup>−6</sup> pF/μm.<ref>{{cite book |first=S. M. |last=Sze |url=https://books.google.com/books?id=o4unkmHBHb8C |title=Physics of Semiconductor Devices |publisher=John Wiley & Sons |year=2007 |isbn=978-0-471-14323-9 }}</ref> There are many materials with lower relative dielectric constants but few of them can be suitably integrated into a manufacturing process. Development efforts have focused primarily on the following classes of materials:

===Fluorine-doped silicon dioxide=== {{Main|Fluorosilicate glass}} By doping SiO<sub>2</sub> with fluorine to produce fluorinated silica glass, the relative dielectric constant is lowered from 3.9 to 3.5.<ref>{{cite journal|doi=10.1016/S0167-9317(01)00586-X|title=Integration of fluorine-doped silicon oxide in copper pilot line for 0.12-μm technology|year=2002|last1=Reynard|first1=J|journal=Microelectronic Engineering|volume=60|issue=1–2|page=113 }}</ref> Fluorine-doped oxide materials were used for the 180 nm and 130 nm technology nodes.<ref name=Ozin2006>{{cite journal |title=Materials chemistry for low-k materials |issue=3 |journal=Materials Today |volume=9 |pages=22–31 |language=en |doi=10.1016/S1369-7021(06)71387-6 |date=1 March 2006|last1=Hatton |first1=Benjamin D. |last2=Landskron |first2=Kai |last3=Hunks |first3=William J. |last4=Bennett |first4=Mark R. |last5=Shukaris |first5=Donna |last6=Perovic |first6=Douglas D. |last7=Ozin |first7=Geoffrey A. |doi-access=free }}</ref>

===Organosilicate glass or OSG (Carbon-doped oxide or CDO)=== By doping SiO<sub>2</sub> with carbon, one can lower the relative dielectric constant to 3.0, the density to 1.4 g/cm<sup>3</sup> and the thermal conductivity to 0.39 W/(m*K). The semiconductor industry has been using the organosilicate glass dielectrics since the 90 nm technology node.<ref name=Maex2004 />

===Porous silicon dioxide=== Various methods may be employed to create voids or pores in a silicon dioxide dielectric.<ref name=Ozin2006 /> Voids can have a relative dielectric constant of nearly 1, thus the dielectric constant of the porous material may be reduced by increasing the porosity of the film. Relative dielectric constants lower than 2.0 have been reported. Integration difficulties related to porous silicon dioxide implementation include low mechanical strength and difficult integration with etch and polish processes.

===Porous organosilicate glass (carbon-doped oxide)=== Porous organosilicate materials are usually obtained by a two-step procedure<ref name="Maex2004">{{cite journal |last1=Shamiryan |first1=D. |last2=Abell |first2=T. |last3=Iacopi |first3=F. |last4=Maex |first4=K. |title=Low-k dielectric materials |journal=Materials Today |volume=7 |pages=34–39 |doi=10.1016/S1369-7021(04)00053-7 |year=2004 |doi-access=free }}</ref> where the first step consists of the co-deposition of a labile organic phase (known as porogen) together with an organosilicate phase resulting in an organic-inorganic hybrid material. In the second step, the organic phase is decomposed by UV curing or annealing at a temperature of up to 400&nbsp;°C, leaving behind pores in the organosilicate low-κ materials. Porous organosilicate glasses have been employed since the 45 nm technology node.<ref name="Dubois2010">{{cite journal |last1=Volksen |first1=W. |last2=Miller |first2=R.D. |last3=Dubois |first3=G. |title=Low Dielectric Constant Materials |journal=Chemical Reviews |date=2010 |volume=110 |issue=1 |pages=56–110 |doi=10.1021/cr9002819 |pmid=19961181 |s2cid=32675222 }}</ref>

===Spin-on organic polymeric dielectrics=== Polymeric dielectrics are generally deposited by a spin-on approach, which is traditionally used for the deposition of photoresist materials, rather than chemical vapor deposition. Integration difficulties include low mechanical strength, coefficient of thermal expansion (CTE) mismatch and thermal stability. Some examples of spin-on organic low-κ polymers are polyimide, polynorbornenes, benzocyclobutene, and PTFE.

===Spin-on silicon based polymeric dielectric=== There are two kinds of silicon based polymeric dielectric materials, hydrogen silsesquioxane and methylsilsesquioxane.

===Air gaps=== The ultimate low-κ material is air with a relative permittivity value of ~1.0. However, the placement of air gaps between the conducting wires compromises the mechanical stability of the integrated circuit making it impractical to build an IC consisting entirely of air as the insulating material. Nevertheless, the strategic placement of air gaps can improve the chip's electrical performance without compromising critically its durability. For example, Intel uses air gaps for two interconnect levels in its 14 nm FinFET technology.<ref>{{cite web |last1=James |first1=Dick |title=IEDM – Monday was FinFET Day |url=https://www.chipworks.com/about-chipworks/overview/blog/iedm-–-monday-was-finfet-day |website=Chipworks.com |accessdate=9 December 2018}}</ref>

==See also== *Dielectric *High-κ dielectric *Relative static permittivity

==References== {{reflist}}

==External links== *[https://web.archive.org/web/20041010091327/http://nepp.nasa.gov/index_nasa.cfm/934/ Nasa on Low-k] *[https://web.archive.org/web/20070315202755/http://www.gaas.org/Digests/2002/PDF/01c.pdf The evolution of interconnect technology for silicon integrated circuitry]

{{DEFAULTSORT:Low-K Dielectric}} Category:Semiconductor fabrication materials Category:Materials science