{{Short description|Part of manufacturing process used to create integrated circuits}} [[File:Cmos-chip structure in 2000s (en).svg|thumb|Illustration of '''FEOL''' (device generation in the silicon, bottom) and BEOL (depositing metalization layers, middle part) to connect the devices.]] thumb|CMOS fabrication process
The '''front end of line''' ('''FEOL''') is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate.<ref> {{cite book | title = Handbook of Silicon Wafer Cleaning Technology | edition = 2nd | author = Karen A. Reinhardt and Werner Kern | publisher = William Andrew | year = 2008 | isbn = 978-0-8155-1554-8 | page = 202 | url = https://books.google.com/books?id=UPaD8JUCKr0C&pg=PA202 }}</ref> FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.<ref>{{Cite web |date=2019-02-22 |title=FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation {{!}} USJC：United Semiconductor Japan Co., Ltd. |url=https://www.usjpc.com/en/tech-intro-e/process-e/element-e |access-date=2022-09-27 |website=USJC：United Semiconductor Japan Co., Ltd. {{!}} 三重県桑名市の300mm半導体ウェーハ工場を製造拠点にしたファウンドリ専業メーカーです。超低消費電力、不揮発メモリなど先進テクノロジーを世界中のお客様に提供しています。 |language=ja}}</ref>
==Steps== For the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:<ref>{{Cite web |last=Ramsundar |first=Bharath |title=A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics |url=https://deepforest.substack.com/p/a-deep-dive-into-chip-manufacturing |access-date=2022-09-27 |website=deepforest.substack.com |date=26 February 2021 |language=en}}</ref><ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|pages=78–82|chapter=Chap. 2.9.3: FEOL: Creating Devices|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0|s2cid=215840278}}</ref> # Selecting the type of wafer to be used; Chemical-mechanical planarization (CMP) and cleaning of the wafer. # Shallow trench isolation (STI) (or LOCOS in early processes with feature size > 0.25 μm); # Well formation; # Gate module formation; # Source and drain module formation.
Finally, the surface is treated to prepare the contacts for the subsequent metallization. This concludes the FEOL process, that is, all devices have been built.<ref name="Layout_book" />
Following these steps, the devices must be connected electrically as per the nets to build the electrical circuit. This is done in the back end of line (BEOL). BEOL is thus the second portion of IC fabrication where the individual devices are connected.<ref name="Layout_book" />
==See also== *Back end of line (BEOL) *Integrated circuit
==References== {{Reflist}}
==Further reading== *"CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. {{ISBN|978-0-470-88132-3}}. [https://books.google.com/books?id=kxYhNrOKuJQC&pg=PA177&dq=FEOL pages 177-178] (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration) * [https://www.ifte.de/books/pd/index.html "Fundamentals of Layout Design for Electronic Circuits"], by Lienig, Scheible, Springer, {{doi|10.1007/978-3-030-39284-0}}{{ISBN|978-3-030-39284-0}}, 2020. [https://link.springer.com/chapter/10.1007/978-3-030-39284-0_2 Chapter 2: Technology Know-How: From Silicon to Devices], pages 78-82 (2.9.3 FEOL: Creating Devices)
{{DEFAULTSORT:Feol}} Category:Electronics manufacturing Category:Semiconductor device fabrication