Circuit underutilization

{{Short description|Not using the area or components of an integrated circuit to full efficiency}} {{Use dmy dates|date=May 2019|cs1-dates=y}} {{Use American English|date=March 2019}} {{dablink|Not to be confused with Circuit minimization for Boolean functions, which is logical optimization rather than physical.}}

'''Circuit underutilization''' also '''chip underutilization''', '''programmable circuit underutilization''', '''gate underutilization''', '''logic block underutilization''' refers to a physical incomplete utility of semiconductor grade silicon on a standardized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or a CPLD.

==Gate array== In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.<ref name="chipdes">{{Cite web|url=http://chipdesignmag.com/display.php?articleId=386|title=Chip Design » The Death of the Structured ASIC by Bob Zeidman, president, Zeidman Technologies|website=chipdesignmag.com|language=en|access-date=2018-10-07}}</ref>

==FPGA== Due to the design components of field-programmable gate array into logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.<ref>{{cite book |citeseerx=10.1.1.52.3689 |title=Designing for High Speed-Performance in CPLDs and FPGAs |first1=Zeljko |last1=Zilic |first2=Guy |last2=Lemieux |first3=Kelvin |last3=Loveless |first4=Stephen |last4=Brown |first5=Zvonko |last5=Vranesic |date=June 1995 |work=Proceeding of the Third Canadian Workshop on FPGAs }}</ref> Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them,<ref name="chipdes"/> resulting in 40 times less density than of standard cell ASICs.

==See also== * Circuit minimization * Don't-care condition

==References== {{reflist}}