{{Short description|Family of microprocessors}} {{refimprove|date=October 2021}} {{Infobox CPU architecture | name = TigerSHARC | designer = Analog Devices | bits = 32-bit | introduced = {{Start date and age|2000}} | version = | design = DSP/RISC | type = Load–store | encoding = ? | branching = ? | endianness = ? | extensions = | open = | registers = 2 × 32 × 32-bit address registers | gpr = 2 × 32 × 32-bit registers (addressable in 16-bit parts) | fpr = }} '''TigerSHARC''' refers to a family of microprocessors currently manufactured by Analog Devices Inc (ADI). It is superscalar and features data-parallelism in the form of short-vector SIMD and subword (16-bit) parallelism (SWAR). It consists of:<ref>{{cite web |last1=Fridman |first1=Jose |last2=Greenfield |first2=Zvi |title=THE TIGERSHARC DSP ARCHITECTURE |url=https://www.ece.ucdavis.edu/~akella/270W05/reading/tigersharc%20technical%20paper.pdf |date=2000}}</ref> * Two separate computation blocks (CompBlocks) each with 32 general-purpose registers and their own ALU, multiplier, and shifter; 256-bit read and 128-bit write bus access * Two integer ALUs (JALU, KALU) each with 32 registers; mainly intended for address generation, but is also capable of general integer arithmetic; 32-bit data bus * A sequencer with 128-entry 4-way associative branch target buffer; 128-bit data bus * Three separate internal memory banks (SRAM) * External port with DMA
== See also == *SHARC *Blackfin
== References == {{Reflist}}
== External links == *[http://www.analog.com/en/processors-dsp/tigersharc/products/index.html TigerSHARC processor website]
Category:Digital signal processors Category:VLIW microprocessors
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