A test register, in the Intel 80386 and Intel 80486 processors, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. Regular programs don't usually require these registers to work. With the Pentium, the test registers were replaced by a variety of model-specific registers (MSRs).[1]

In the 80386, two test registers, TR6 and TR7, were provided for the purpose of TLB testing. TR6 was the test command register, and TR7 was the test data register. The 80486 provided three additional registers, TR3, TR4 and TR5, for testing of the L1 cache. TR3 was a data register, TR4 was an address register and TR5 was a command register. These registers were accessed by variants of the MOV instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both real-address mode and protected mode. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at privilege level 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on most CPUs newer than 80486.

The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as 0F 26 /r (with r/m being the GPR, and reg being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as 0F 24 /r (with r/m being the GPR, and reg being the test register).[2] Only register-register moves are supported - as such, the "mod" field (top 2 bits) of the instruction's ModR/M byte should be set to 11b. (Setting the "mod" field of the ModR/M byte to anything else than 11b results in undefined behaviour, with different behaviour observed on different processors.[3])

The test registers and/or associated opcodes were supported in the following x86 processors:

Processorscolspan="3"Cache Test RegistersTLB Test Registers
TR0TR1TR2TR3TR4TR5TR6TR7
Intel 386 (all models)colspan="3"colspan="1"colspan="2"colspan="2"
Intel 486 (all models)colspan="3"colspan="3"colspan="2"
AMD 386 (all models)
AMD Élan SC3xx		colspan="3"colspan="2"colspan="2"
AMD 486 (all models)
AMD 5x86
AMD Élan SC4xx,SC5xx		colspan="3"colspan="3"colspan="2"
IBM 386SLC
IBM BL486SLC2/SX2/SX3		colspan="3"colspan="3"colspan="2"
C&T Super386colspan="3"colspan="3"colspan="2"
NexGen Nx586colspan="3"colspan="3"colspan="2"
Cyrix[a] 486 (all models[b])colspan="3"colspan="3"colspan="2"
Cyrix 5x86colspan="2"colspan="3"colspan="2"
Cyrix 6x86colspan="2"colspan="3"colspan="2"
Cyrix 6x86MX, MIIcolspan="2"colspan="3"colspan="2"
VIA Cyrix III[c]colspan="2"colspan="3"colspan="2"
Cyrix MediaGX
NatSemi Geode GX		colspan="2"colspan="3"colspan="2"
NatSemi Geode GX2
AMD Geode GX, LX		colspan="8"
IDT WinChip (all models)colspan="8"
Intel Quark X1000colspan="3"colspan="3"colspan="2"
  1. ^ Cyrix manufacturing partner CPU models from IBM, TI and ST also all supported the same test registers as their corresponding Cyrix-branded CPU models.
  2. ^ SoCs based on the Cyrix-derived ST486 CPU core also supported the same set of test registers as the Cyrix 486 - such SoCs include e.g. STPC Atlas and ZFMicro ZFx86.[4]
  3. ^ "Joshua" core only. "Samuel" core variants of Cyrix III did not support the TRx test registers.

See also

References

  1. ^ Intel, Pentium® Processor Family Developer’s Manual, order no. 241428-005, 1997, section 16.1.2, page 442 - provides a list of Pentium MSRs that provide the same functionality as the 386/486 TRx registers.
  2. ^ Introduction to the 80386 Including the 80386 Data Sheet. Intel. April 1986. p. 122.
  3. ^ Robert L. Hummel, PC Magazine Programmer's Technical Reference, 1992, ISBN 1-56276-016-5, page 476.
  4. ^ ZFMicro, ZFx86 Data Book 1.0 Rev D, 5 June 2006, page 101