{{Short description|Chip-to-chip, channelized, packet interface}} '''SPI-3''' or System Packet Interface Level 3 is the name of a chip-to-chip, channelized, packet interface widely used in high-speed communications devices. It was proposed by PMC-Sierra based on their PL-3 interface to the Optical Internetworking Forum and adopted in June 2000. PL-3 was developed by PMC-Sierra in conjunction with the SATURN Development Group.
==Applications== It was designed to be used in systems that support OC-48 SONET interfaces . A typical application of SPI-3 is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace.
==Technical details== The interface consists of (per direction): * 32 TTL signals for the data path * 8 TTL signals for control * one TTL signal for clock * 8 TTL signals for optional additional multi-channel status
There are several clocking options. The interface operates around 100 MHz. Implementations of SPI-3 (PL-3) have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets.
==SPI-3 in the marketplace== SPI-3 (and PL-3) was a highly successful interface with many semiconductor devices produced to it.
==See also== * System Packet Interface * SPI-4.2
==External links== * [http://www.oiforum.com/public/impagreements.html OIF Interoperability Agreements] {{Webarchive|url=https://web.archive.org/web/20051025083456/http://www.oiforum.com/public/impagreements.html |date=2005-10-25 }}
{{DEFAULTSORT:Spi-3}} Category:Network protocols
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