RH-32

{{1r|date=May 2015}}The '''RH-32''' was a radiation-hardened 32-bit MIPS R3000 based microprocessor chipset developed by the USAF Rome Laboratories<ref>Schechter, Joanne. "Will commercial strategy deliver cost, time savings? (military microprocessors)(includes related article on SGS-Thomson's new transputers)." EDN. Canon Communications L.L.C. 1991. http://www.highbeam.com/doc/1G1-11230801.html {{Webarchive|url=https://web.archive.org/web/20150924052938/http://www.highbeam.com/doc/1G1-11230801.html |date=2015-09-24 }}</ref> for the Ballistic Missile Defense Agency, and produced by Honeywell (later, TRW) for Aerospace applications. It achieves a throughput of 20 MIPS. It was a three-chip set, consisting of Central Processing Unit, Floating Point Unit, and Cache Memory.<ref name= "IEEE.1997">{{cite book|author= G.R. Brown, L.F. Hoffmann, S.C. Leavy, J.A. Mogensen, J. Brichacek|title= 1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference|chapter= Honeywell radiation hardened 32-bit processor central processing unit, floating point processor, and cache memory dose rate and single event effects test results|date= 1997-07-24|publisher= IEEE|pages= 110–115|doi= 10.1109/REDW.1997.629808|isbn= 0-7803-4061-2|s2cid= 60521143|language= en|quote= }}</ref>

== References == {{reflist}} {{Honeywell}} Category:Honeywell Category:32-bit microprocessors Category:MIPS implementations Category:Radiation-hardened microprocessors