{{Short description|Type of computer memory}} {{Hatnote|Not to be confused with [[ECC memory]], although memory modules often use both technologies.}} [[File:Micron MTC40F204681RC48BA1R 20240407 076.jpg|thumb|right|upright=1.4|One 64 GiB [[DDR5]]-4800 ECC 1.1 V registered [[DIMM]] (RDIMM)]] [[File:16 GiB-DDR4-RAM-Riegel RAM019FIX Small Crop 90 PCNT.png|thumb|Example of an unregistered DIMM (UDIMM)]] '''Registered memory''' (also called '''buffered memory''') is [[computer memory]] that has a [[Hardware register|register]] between the [[Dynamic random access memory|DRAM]] modules and the system's [[memory controller]]. A registered memory module places less electrical load on a memory controller than an unregistered one because the register locally re-drives the signal. Registered memory allows a computer system to remain stable with more [[memory module]]s than it would have otherwise.
When conventional memory is compared with registered memory, conventional memory is usually referred to as '''unbuffered memory''' or '''unregistered memory'''. When registered memory is manufactured as a [[dual in-line memory module]] (DIMM), it is called an '''RDIMM'''. Similarly, an unregistered DIMM is called a '''UDIMM''' or simply "DIMM".
Registered memory is often more expensive because of the additional [[Electrical component|circuitry]] required and [[Economies of scale|lower number of units sold]], so it is usually found only in applications where the need for [[scalability]] and [[Robustness (computer science)|robustness]] outweighs the need for a low price{{snd}} for example, registered memory is usually used in [[Server (computing)|server]]s.
Although most registered memory modules also feature [[error-correcting code memory]] (ECC), it is also possible for registered memory modules to not be error-correcting or vice versa. Unregistered ECC memory is supported and used in [[workstation]] or entry-level server motherboards that do not support very large amounts of memory.<ref>{{cite web |title=ASUS P9D-V |url=https://theretroweb.com/motherboards/s/asus-p9d-v |website=The Retro Web |quote=(webpage) RAM Type: DDR3 UDIMM ECC (linked manual) Memory Type DDR3 1333/1600 ECC UDIMM}}</ref>
==Performance== Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one [[clock cycle]] behind the equivalent unregistered DRAM. With [[SDRAM]], this only applies to the first cycle of a burst.
However, this performance penalty is not universal. There are many other factors involved in memory access speed. For example, the Intel [[Westmere (microarchitecture)|Westmere]] 5600 series of processors access memory using [[Interleaved memory|interleaving]], wherein memory access is distributed across three channels. If two memory DIMMs are used per channel, there is a reduction of maximum [[memory bandwidth]] for this configuration with UDIMM by some 5% in comparison to RDIMM.<ref> {{cite web | url = https://sp.ts.fujitsu.com/dmsp/Publications/public/wp-westmere-ep-memory-performance-ww-en.pdf | title = WHITE PAPER - FUJITSU PRIMERGY SERVERS - MEMORY PERFORMANCE OF XEON 5600 (WESTMERE-EP) BASED SYSTEMS | page = 17 | date = 2011-06-06 | version = 2.0 | website = Fujitsu Global | publisher = Fujitsu Technology Solutions GmbH | access-date = 2023-05-20 | quote = ''This results in a reduction of maximum memory bandwidth for 2DPC configurations with UDIMM by some 5% in comparison to RDIMM.'' }}.</ref><ref> {{cite web | url = https://community.spiceworks.com/t/difference-between-rdimm-and-udimm/1008277 | title = How to: Difference between RDIMM and UDIMM | last = Florin | first = Anghel | date = 2013-10-22 | website = Spiceworks | access-date = 2023-05-20 | quote = ''But when you go to 2 DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller use something called a “2T” or “2N” timing for UDIMMs.<br />Consequently every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs.'' }}</ref>
==Compatibility== Usually, the [[motherboard]] must match the memory type; as a result, registered memory will not work in a motherboard not designed for it, and vice versa. Some PC motherboards accept or require registered memory, but registered and unregistered memory modules cannot be mixed.<ref> {{cite web | url = https://i.dell.com/sites/doccontent/business/solutions/whitepapers/en/Documents/server-pedge-installing-upgrading-memory-11g.pdf | title = Dell servers example | website = Dell | archive-url = https://web.archive.org/web/20201112034337/http://www.dell.com/downloads/global/products/pedge/en/server-pedge-installing-upgrading-memory-11g.pdf | archive-date = 2020-11-12 | url-status = live }}</ref> There is much confusion between ''registered'' and ''ECC'' memory; it is widely thought that ECC memory (which may or may not be registered) will not work at all in a motherboard without ECC support, not even without providing the ECC functionality, although the compatibility issues actually arise when trying to use ''registered'' memory (which often supports ECC and is described as ECC RAM) in a PC motherboard that does not support it.
== Buffered memory types == [[File:Clocked Unbuffered DIMM.svg|thumb|upright=0.75|Clocked Unbuffered DIMM, for comparison with later types]] '''Clocked Unbuffered DIMM''' ('''{{vanchor|CUDIMM}}''') and '''Clocked Small Outline DIMM''' ('''{{vanchor|CSODIMM}}''') modules include a buffer on the clock bus, but are otherwise unbuffered. This enhances clock integrity at higher speeds at relatively little added cost. They were introduced for [[DDR5]] in 2024.<ref>{{cite web | url = https://www.anandtech.com/show/21455/making-desktop-ddr5-even-faster-cudimms-debut-at-computex | archive-url = https://web.archive.org/web/20240621150743/https://www.anandtech.com/show/21455/making-desktop-ddr5-even-faster-cudimms-debut-at-computex | url-status = dead | archive-date = June 21, 2024 | title = CUDIMM Standard Set to Make Desktop Memory a Bit Smarter and a Lot More Robust | author = Ryan Smith & Anton Shilov | date = 2024-06-21 | publisher = AnandTech | access-date = 2025-01-03}} </ref> The clock buffer is also called a '''client clock driver''' (CKD). Systems that do not support CUDIMM/CSODIMM can still use them after a BIOS update that allows for using the modules in pass-through mode.<ref>{{cite web |title=What is a CUDIMM / CSODIMM? - Kingston Technology |url=https://www.kingston.com/en/blog/system-builder/what-is-a-cudimm-csodimm |website=Kingston Technology Company |language=en}}</ref>
{{clear}} [[File:20210402 Registered versus load-reduced DIMM memory.svg|thumb| upright=1.5 | Comparison: Registered Memory (R-DIMM) and Load Reduced DIMM (LR-DIMM)<ref>{{cite magazine | last1=Deffree | first1=Suzanne | title=Basics of LRDIMM | url=https://www.edn.com/basics-of-lrdimm/ | magazine=EDN | date=September 20, 2011 | archive-url=https://web.archive.org/web/20210402174928/https://www.edn.com/basics-of-lrdimm/ | archive-date=April 2, 2021 | url-status=live}}</ref> ]] {{Anchor|RDIMM}}'''Registered (Buffered) DIMM (R-DIMM or RDIMM)''' modules insert a [[Digital buffer|buffer]] between the pins of the clock, command and address buses on the DIMM and the memory chips. A high-capacity DIMM might have numerous memory chips, each of which must receive the [[memory address]], and their combined [[Parasitic capacitance|input capacitance]] limits the speed at which the memory bus can operate. By redistributing the command and address signals within the R-DIMM, this allows more chips to be connected to the memory bus.<ref name="anandtechlr">{{cite web | url = https://www.anandtech.com/show/6068/lrdimms-rdimms-supermicros-latest-twin/2 | archive-url = https://archive.today/20140908224719/http://www.anandtech.com/show/6068/lrdimms-rdimms-supermicros-latest-twin/2 | url-status = dead | archive-date = September 8, 2014 | title = LRDIMMs, RDIMMs, and Supermicro's Latest Twin | date = 2012-08-03 | accessdate = 2025-01-03 | author = Johan De Gelas | publisher = [[AnandTech]] }}</ref> The cost is increased [[memory latency]], as a result of one{{citation needed|date=March 2021}} additional clock cycle required for the address to traverse the additional buffer. Early registered RAM modules were physically incompatible with unregistered RAM modules, but the two variants of SDRAM R-DIMMs are mechanically interchangeable, and some motherboards may support both types.<ref name="wikichip">{{cite web | url = https://en.wikichip.org/wiki/amd/packages/socket_swrx8 | title = Socket sWRX8 - AMD | archive-url = https://web.archive.org/web/20220626051051/https://en.wikichip.org/wiki/amd/packages/socket_swrx8 | archive-date = 2022-06-26 }}</ref>
{{Anchor|LRDIMM}}'''Load Reduced DIMM (LR-DIMM or LRDIMM)''' modules are similar to R-DIMMs, but add a buffer to the data lines as well. In other words, LR-DIMMs buffer both control and data lines while keeping the parallel nature of all signals. As a result, LR-DIMMs provide large overall maximum memory capacities, while avoiding the performance and power consumption problems of FB-DIMMs, induced by the required conversion between serial and parallel signal forms.<ref name="anandtechlr" /><ref name="lrdimm">{{cite web | url = https://www.simmtester.com/News/PublicationArticle/167 | title = What is LR-DIMM, LRDIMM Memory? (Load-Reduce DIMM) | accessdate = 2014-08-29 | website = simmtester.com }}</ref>
{{clear}} {{Anchor|FBDIMM}}'''[[Fully Buffered DIMM]] (FB-DIMM)''' modules increase maximum memory capacities in large systems even more, using a more complex buffer chip to translate between the wide bus of standard SDRAM chips and a narrow, high-speed serial memory bus. In other words, all control, address and data transfers to FB-DIMMs are performed in a serial fashion, while the additional logic present on each FB-DIMM transforms serial inputs into parallel signals required to drive memory chips.<ref name="lrdimm" /> By reducing the number of pins required per memory bus, CPUs could support more memory buses, allowing higher total [[memory bandwidth]] and capacity. Unfortunately, the translation further increased memory latency, and the complex high-speed buffer chips used significant power and generated a lot of heat.
Both FB-DIMMs and LR-DIMMs are designed primarily to minimize the load that a memory module presents to the memory bus. They are not compatible with R-DIMMs, and motherboards that require them usually will not allow mixing types of memory modules.
{{Anchor|HB-DIMM}} '''High bandwidth DIMM (HB-DIMM)''' was proposed by AMD to double the bandwidth of DDR5 memory in 2025. In a HB-DIMM, the register chip doubles as a multiplexer that forwards the signal into one of the two connected independently addressible channels. As a result, two channels (four subchannels) can fit onto one DIMM.<ref>{{cite web |title=New AMD patent details high bandwidth DIMM design that doubles DDR5 data rates |url=https://www.techradar.com/pro/amd-wants-to-double-ddr5-memory-bandwidth-using-clever-trick-patent-reveals-but-this-is-no-socamm-rival-and-amds-previous-memory-project-didnt-end-well |website=TechRadar |language=en |date=2 October 2025}}</ref>
== References == {{Commons|Category:CUDIMM}} {{Commons|Category:RDIMM}} {{Commons|Category:FB-DIMM}} {{Reflist}}
== Further reading == {{refbegin}} * {{cite web|url=https://www.ti.com/lit/ds/symlink/sn74sstub32864.pdf|title=SN74SSTUB32864 25-BIT CONFIGURABLE REGISTERED BUFFER|author=Texas Instrument|date=2006}} – a typical register designed for DDR2 {{refend}} [[Category:Computer memory]]