{{Short description|Microprocessor developed by Hewlett-Packard}} thumb|right|A PA-7100LC microprocessor.
The '''PA-7100LC''' is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It is also known as the '''PCX-L''', and by its code-name, ''Hummingbird''. It was designed as a low-cost microprocessor for low-end systems.<ref name="pcw199404_processors">{{ cite magazine | title=Six of the best | magazine=Personal Computer World | date=April 1994 | last1=Rockman | first1=Simon | pages=464-468,470,472 }}</ref> The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz clock rates. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
right|thumb|Die shot of PA-7100LC The PA-7100LC was based on the PA-7100. Major improvements were improved superscalar execution and an extra integer unit. The PA-7100LC also implemented architectural improvements including the MAX-1 multimedia instructions, uncacheable memory pages, and bi-endian support. Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load–store unit operations, or an integer and a load or a store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100.
A number of modifications were made to circuits derived from the PA-7100LC. Prominently, the floating-point unit multiplier was modified to take up less area by halving the tree of carry-save adders that summed the partial products of the mantissa. This simplification left the latency of single precision multiplies unchanged (two cycles), but increased the latency of double-precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent. Integrated on-die to lower costs is a memory controller that supports up to 2 GB of memory and an I/O controller.
The organization of the caches is different from that of most HP-designed PA-RISC CPUs. The large external instruction and data caches have been replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache. The external cache is unified, containing both instructions and data.<ref name="pcw199404_processors"/>
The PA-7100LC consists of 900,000 transistors and measures 14.2 by 14.2 mm for an area of 201.64 mm<sup>2</sup>. It was fabricated by HP in their 0.8 μm three-level metal CMOS26B process. The PA-7100LC is packaged in a 432-pin ceramic pin grid array.
==PA-7300LC== thumb|right|A PA-7300LC microprocessor. The '''PA-7300LC''' was a further development of the PA-7100LC. It was introduced in mid-1996 as a low-end to mid-range microprocessor complementing the high-end PA-8000 in HP's workstations and servers. The PA-7300LC integrates an improved PA-7100LC, 64 KB instruction and data caches, L2 cache controller, memory controller and a GSC bus controller onto a single chip. It was the first PA-RISC microprocessor to include any significant amount of on-chip cache. The L2 unified cache was optional and could be protected by parity. It could be built from register-to-register, flow-through or asynchronous SRAM.
right|thumb|Die shot of PA-7300LC. The PA-7300LC contained 9.2 million transistors, of which 1.2 million are used in logic and 8 million are used in the caches; and measured 15.3 by 17.0 mm for an area of 260.1 mm<sup>2</sup>. It was fabricated by HP in their CMOS14C process, a 0.5 μm, 3.3 V, four-layer-metal CMOS process.
This design includes a famous "silicon doodle" of a velociraptor dinosaur (visible here in upper right corner of the die shot image).<ref>{{Cite web |title=Molecular Expressions: The Silicon Zoo - Velociraptor |url=https://micro.magnet.fsu.edu/creatures/pages/velo.html |access-date=2024-04-17 |website=micro.magnet.fsu.edu}}</ref> {{clear}}
==References== {{reflist}} * Gwennap, Linley (24 January 1994). "New PA-RISC Processor Decodes MPEG Video". ''Microprocessor Report''. pp. 16–17. * Gwennap, Linley (13 November 1995). "Integrated PA-7300LC Powers HP Midrange". ''Microprocessor Report''. * Hollenbeck, D. et al. (1996). "PA7300LC integrates cache for cost/performance". ''COMPCON '96 Digest of Technical Papers''. * Josephson, D.; Storey, M.; Dixon, D. (1995). "Microprocessor IDDQ testing: a case study". ''IEEE Design & Test of Computers''. * Josephson, D.D.; Dixon D.J.; Arnold B.J. (1993). "Test features of HP PA7100LC processor". ''Proceedings of IEEE International Test Conference''. * Kever, W. et al. (1997). "A 200 MHz RISC microprocessor with 128 kB on-chip caches". ''ISSCC Digest of Technical Papers''. * Knebel, P. et al. (1993). "HP's PA7100LC: a low-cost superscalar PA-RISC processor". ''COMPCON Spring '93 Digest of Papers''. * Knebel, P. et al. (1995). "[http://www.hpl.hp.com/hpjournal/95apr/apr95a2a.pdf The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment]". ''hpjournal Apr 1995''. * Lee, R.B. (1995). "Realtime MPEG video via software decomposition on a PA-RISC processor". * Lee, R.B. (April 1995). "Accelerating multimedia with enhanced microprocessors". ''IEEE Micro''. * Meneghini, T.; Josephson, D. (1997). "IDDQ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches". ''IEEE International Workshop on IDDQ Digest of Technical Papers''. * Undy, S. et al. (April 1994). "A low-cost graphics and multimedia workstation chip set". ''IEEE Micro''. * [http://www.openpa.net/pa-risc_processor_pa-7100lc.html PA-7100LC PA-RISC Processor] ''OpenPA.net'' * [http://www.openpa.net/pa-risc_processor_pa-7300lc.html PA-7300LC PA-RISC Processor] ''OpenPA.net''
== External links == [https://m.youtube.com/watch?v=75BjwYgFaDQ Hummingbird: A Low-Cost Superscaler PA_RISC Processor, lecture by Stephen Undy]
{{Hewlett-Packard}}
Category:HP microprocessors Category:Superscalar microprocessors Category:32-bit microprocessors