Machine Check Architecture

{{Multiple issues| {{More citations needed|date=December 2007}} {{Update|date=February 2014}} }}

In computing, '''Machine Check Architecture''' ('''MCA''') is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system.

Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors.<ref name="Intel Manual 3B 2">{{cite book |date=September 2023 |url=https://www.intel.com/content/www/us/en/content-details/789580/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-3b-system-programming-guide-part-2.html |title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 |publisher=Intel Corporation |page=16{{hyphen}}1 |access-date=September 19, 2025 }}</ref> It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.<ref name="Intel Manual 3B 2" />

==References== {{Reflist}}

==External links== * [http://www.microsoft.com/whdc/system/platform/64bit/MCAsupport.mspx Microsoft's article on Itanium's MCA] * [http://www.mcelog.org/ Linux x86 daemon for processing of machine checks]

Category:Computer architecture Category:X86 architecture