| Produced-start | 2010 (age 16)[1] |
|---|---|
| Slowest | 750 |
| Fastest | 1 |
| Slow-unit | MHz |
| Fast-unit | GHz |
| Fsb-slowest | 2 |
| Fsb-slow-unit | Gbps |
| Size-from | 100 mm² |
| Designfirm | MCST |
| Manuf 1 | TSMC |
| Pack 1 | FPGA |
| Arch | SPARC V9 |
| Numcores | 4 |
| Predecessor | MCST-R500S |
| Successor | MCST-R2000 |
| Application | Embedded |
| L1cache | 48 KB |
| L2cache | 2 MB |
The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by MCST.[2]
During development this microprocessor was designated as MCST-4R.[1]
MCST R1000 Highlights
- implements the SPARC V9 instruction set architecture (ISA)
- quad-core
- core specifications:
- in-order, dual-issue superscalar
- 7-stage integer pipeline
- 9-stage floating-point pipeline
- VIS extensions 1 and 2
- Multiply–accumulate unit
- 16 KB L1 instruction cache (parity protection)
- 32 KB L1 data cache (parity protection)
- size 7.6 mm2
- shared 2MB L2 cache (ECC protection)
- integrated memory controller
- integrated ccNUMA controller
- 1 GHz clock rate
- 90 nm process
- die size 128 mm2
- ~150 million transistors
- power consumption 15W
References
- ^ "Участие ЗАО «МЦСТ» и ОАО «ИНЭУМ им.И.С.Брука» в международной выставке “ChipExpo – 2011” (итоги участия)", "ru:Новости" (in Russian), MCST, archived from the original on 2011-05-11, retrieved 2011-12-06
- ^ "Система на кристалле "МЦСТ-4R"" (in Russian), MCST, archived from the original on 2011-09-27, retrieved 2011-11-18