'''Fault grading''' is a procedure that rates testability by relating the number of fabrication defects that can in fact be detected with a test vector set under consideration to the total number of conceivable faults.
It is used for refining both the test circuitry and the test patterns iteratively, until a satisfactory fault coverage is obtained.<ref>{{citation|title = Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication|first = Hubert| last = Kaeslin|page = 24|publisher = Cambridge University Press|url = https://books.google.com/books?id=gdRStcYgf2oC&dq=%22fault+grading%22&pg=PA24|isbn = 9780521882675|date = 2008-04-28}}</ref>
==See also== * Automatic test pattern generation * Design for Test
==References== <references/>
Category:Hardware testing