AMD CDNA
CreatedNov 16, 2020
DesignfirmAMD
Process
PredecessorGCN 5

CDNA (Compute DNA) is a compute-centered graphics processing unit (GPU) microarchitecture designed by AMD for datacenters. Mostly used in the AMD Instinct line of data center graphics cards, CDNA is a successor to the Graphics Core Next (GCN) microarchitecture; the other successor being RDNA (Radeon DNA), a consumer graphics focused microarchitecture.

The first generation of CDNA was announced on March 5th, 2020,[2] and was featured in the AMD Instinct MI100, launched November 16th, 2020.[3] This is CDNA 1's only produced product, manufactured on TSMC's N7 FinFET process.

The second iteration of the CDNA line implemented a multi-chip module (MCM) approach, differing from its predecessor's monolithic approach. Featured in the AMD Instinct MI250X and MI250, this MCM design used an elevated fanout bridge (EFB)[4] to connect the dies. These two products were announced November 8th, 2021, and launched November 11th. The CDNA 2 line includes an additional latecomer using a monolithic design, the MI210.[5] The MI250X and MI250 were the first AMD products to use the Open Compute Project (OCP)'s OCP Accelerator Module (OAM) socket form factor. Lower wattage PCIe versions are available.

The third iteration of CDNA switches to a MCM design utilizing different chiplets manufactured on multiple nodes. Currently consisting of the MI300X and MI300A, this product contains 15 unique dies and is connected with advanced 3D packaging techniques. The MI300 series was announced on January 5, 2023, and launched in H2 2023.

CDNA 1

AMD CDNA 1
CreatedNov 16, 2020
ProcessTSMC N7 (FinFET)
PredecessorGCN 5
SuccessorCDNA 2

The CDNA family consists of one die, named Arcturus. The die is 750 square millimetres, contains 25.6 billion transistors and is manufactured on TSMC's N7 node.[6] The Arcturus die possesses 120 compute units and a 4096-bit memory bus, connected to four HBM2 placements, giving the die 32 GB of memory, and just over 1200 GB/s of memory bandwidth. Compared to its predecessor, CDNA has removed all hardware related to graphics acceleration. This removal includes but is not limited to: graphics caches, tessellation hardware, render output units (ROPs), and the display engine. CDNA retains the VCN media engine for HEVC, H.264, and VP9 decoding.[7] CDNA has also added dedicated matrix compute hardware, similar to those added in Nvidia's Volta Architecture.

Architecture

The 120 compute units (CUs) are organized into 4 asynchronous compute engines (ACEs), each ACE maintaining its own independent command execution and dispatch. At the CU level, CDNA compute units are organized similarly to GCN units. Each CU contains four SIMD16, that each execute their 64-thread wavefront (Wave64) over four cycles.

Memory system

CDNA has a 20% clock bump for the HBM, resulting in a roughly 200 GB/s bandwidth increase vs. Vega 20 (GCN 5.0). The die has a shared 4 MB L2 cache that puts out 2 KB per clock to the CUs. At the CU level, each CU has its own L1 cache, a local data store (LDS) with 64 KB per CU and a 4 KB global data store (GDS), shared by all CUs. This GDS can be used to store control data, reduction operations or act as a small global shared surface.[7][8]

Experimental PIM implementation

In October 2022, Samsung demonstrated a Processing-In-Memory (PIM) specialized version of the MI100. In December 2022 Samsung showed off a cluster of 96 modified MI100s, boasting large increases in processing throughput for various workloads and significant reduction in power consumption.[9]

Changes from GCN

The individual compute units remain highly similar to GCN but with the addition of 4 matrix units per CU. Support for more datatypes were added, with BF16, INT8 and INT4 being added.[7] For an extensive list of operations utilizing the matrix units and new datatypes, please reference the CDNA ISA Reference Guide.

CDNA 2

AMD CDNA 2
CreatedNov 8, 2021
ProcessTSMC N6
PredecessorCDNA 1
SuccessorCDNA 3

Like CDNA, CDNA 2 also consists of one die, named Aldebaran. This die is estimated to be 790 square millimetres, and contains 28 billion transistors while being manufactured on TSMC's N6 node.[10] The Aldebaran die contains only 112 compute units, a 6.67% decrease from Arcturus. Like the previous generation, this die contains a 4096-bit memory bus, now using HBM2e with a doubling in capacity, up to 64 GB. The largest change in CDNA 2 is the ability for two dies to be placed on the same package. The MI250X consists of 2 Aldebaran dies, 220 CUs (110 per die) and 128 GB of HBM2e. These dies are connected with 4 Infinity Fabric links, and addressed as independent GPUs by the host system.[11]

Architecture

The 112 CUs are organized similarly to CDNA, into 4 asynchronous compute engines, each with 28 CUs, instead of the prior generations 30. Like CDNA, each CU contains four SIMD16 units executing a 64-thread wavefront across 4 cycles. The 4 matrix engines and vector units have added support for full rate FP64, enabling significant uplift over the prior generation.[12] CDNA 2 also revises multiple internal caches, doubling bandwidth across the board.

Memory system

The memory system in CDNA 2 sports across the board improvements. Starting with the move to HBM2e, doubling the quantity to 64 GB, and increasing bandwidth by roughly one third (from ~1200 GB/s to 1600 GB/s).[11] At the cache level. Each GCD has a 16-way, 8 MB L2 cache that is partitioned into 32 slices. This cache puts out 4 KB per clock, 128 B per clock per slice, which is a doubling of the bandwidth from CDNA.[11] Additionally, the 4 KB Global Data Store was removed.[12] All caches, including the L2 and LDS have support added for FP64 data.

Interconnect

CDNA 2 brings forth the first product with multiple GPUs on the same package. The two GPU dies are connected by 4 Infinity Fabric links, with a total bidirectional bandwidth of 400 GB/s.[12] Each die contains 8 Infinity Fabric links, each physically implemented with a 16-lane Infinity Link. When paired with an AMD processor, this will act as Infinity Fabric. if paired with any other x86 processor, this will fallback to 16 lanes of PCIe 4.0.[12]

Changes from CDNA

The largest up front change is the additional of full rate (1:1 compared to non-packed FP32) FP64 support across all compute elements. This results in a 4x increase FP64 matrix calculations, with large increases in FP64 vector calculations.[11] INT32 multiply is also now executed at full rate like INT32 add, unlike the quarter-rate seen in GCN.[13]

Additionally support for packed FP32 operations were added, with opcodes like V_PK_FMA_F32 and V_PK_MUL_F32.[14] Packed FP32 operations can enable up to 2x throughput, but do require code modification (at minimum, recompilation).[11] As with CDNA, for further information on CDNA 2 operations, please reference the CDNA 2 ISA Reference Guide.

Products

AMD Instinct CDNA 2 GPU generations MI-2xx
AcceleratorLaunch dateArchitectureLithographyCompute UnitsMemoryPCIe supportForm factorProcessing powerTBP
SizeTypeBandwidth (GB/s)FP16BF16FP32FP32 matrixFP64 performanceFP64 matrixINT8INT4
MI2102022-03-22[15]CDNA 26 nm10464 GBHBM2E1600181 TFLOPS22.6 TFLOPS45.3 TFLOPS22.6 TFLOPS45.3 TFLOPS181 TOPS300 W
MI2502021-11-08[16]208128 GB3200OAM362.1 TFLOPS45.3 TFLOPS90.5 TFLOPS45.3 TFLOPS90.5 TFLOPS362.1 TOPS560 W
MI250X220383 TFLOPS47.92 TFLOPS95.7 TFLOPS47.9 TFLOPS95.7 TFLOPS383 TOPS560 W

CDNA 3

AMD CDNA 3
CreatedDec 6, 2023
ProcessTSMC N5 & N6
PredecessorCDNA 2

Unlike its predecessors, CDNA 3 consists of multiple dies, used in a multi-chip system, similar to AMD's Zen 2, 3, 4 and 5 line of products. The MI300 package is comparatively massive, with nine chiplets produced on 5 nm, placed on top of four 6 nm chiplets.[17] This is all combined with 128 GB of HBM3, using eight HBM placements.[18] This package contains an estimated 146 billion transistors. It comes in the form of the Instinct MI300X and MI300A, the latter being an APU. These products were launched on December 6, 2023.[19]

The MI300X consists of 8 accelerator complex dies (XCDs) and 4 IO dies (IODs). The MI300A consists of 6 XCDs, 3 core complex dies (CCDs) with 8 Zen 4 cores each running at 3.7 GHz, and 4 IODs. Several MI300As can be used in the same system; for example, Gigabyte makes a quad-socket motherboard intended for four such APUs.[20]

Products

AMD Instinct CDNA 3 GPU generations - MI-3xx
AcceleratorLaunch dateArchitectureLithographyCompute UnitsMemoryPCIe supportForm factorProcessing powerTBP
SizeTypeBandwidth (GB/s)FP16BF16FP32FP32 matrixFP64 performanceFP64 matrixINT8INT4
MI300A2023-12-06[21]CDNA 36 & 5 nm228128 GBHBM353005.0APU SH5 LGA6096 socket980.6 TFLOPS
1961.2 TFLOPS (with Sparsity)		122.6 TFLOPS61.3 TFLOPS122.6 TFLOPS1961.2 TOPS
3922.3 TOPS (with Sparsity)		N/A550 W
760 W (with liquid cooling)
MI300X304192 GBOAM1307.4 TFLOPS
2614.9 TFLOPS (with Sparsity)		163.4 TFLOPS81.7 TFLOPS163.4 TFLOPS2614.9 TOPS
5229.8 TOPS (with Sparsity)		N/A750 W
MI325X2024-10-10[22]256 GBHBM3E6000

CDNA 4

AMD CDNA 4
CreatedJune 12, 2025 (age 1)
ProcessTSMC 3nm (XCD), 6nm FinFET (IOD)
PredecessorCDNA 3

AMD announced the plans for MI350X and MI355X at Advancing AI 2025.[23] The new models come in two forms: the single GPU in the OCP Accelerator Module (OAM) form factor and a water-cooled octo-GPU "platform" designed to fit onto a rack. Both are designed with the UBB (OCP universal baseboard) in mind.[24]

See also

References

  1. ^ Smith, Ryan (June 9, 2022). "AMD: Combining CDNA 3 and Zen 4 for MI300 Data Center APU in 2023". AnandTech. Archived from the original on April 5, 2023. Retrieved December 20, 2022.
  2. ^ Smith, Ryan. "AMD Unveils CDNA GPU Architecture: A Dedicated GPU Architecture for Data Centers". www.anandtech.com. Archived from the original on January 24, 2021. Retrieved 2022-09-20.
  3. ^ "GPU Database: AMD Radeon Instinct MI100". TechPowerUp. Retrieved 2022-09-20.
  4. ^ Smith, Ryan. "AMD Announces Instinct MI200 Accelerator Family: Taking Servers to Exascale and Beyond". www.anandtech.com. Archived from the original on November 8, 2021. Retrieved 2022-09-21.
  5. ^ Smith, Ryan. "AMD Releases Instinct MI210 Accelerator: CDNA 2 On a PCIe Card". www.anandtech.com. Archived from the original on March 7, 2024. Retrieved 2022-09-21.
  6. ^ Kennedy, Patrick (2020-11-16). "AMD Instinct MI100 32GB CDNA GPU Launched". ServeTheHome. Retrieved 2022-09-22.
  7. ^ "AMD CDNA Whitepaper". amd.com. 2020-03-05. Retrieved 2022-09-22.
  8. ^ ""AMD Instinct MI100" Instruction Set Architecture, Reference Guide". developer.amd.com. 2020-12-14. Retrieved 2022-09-22.
  9. ^ Aaron Klotz (2022-12-14). "Samsung Soups Up 96 AMD MI100 GPUs With Radical Computational Memory". Tom's Hardware. Retrieved 2022-12-23.
  10. ^ Anton Shilov (2021-11-17). "AMD's Instinct MI250X OAM Card Pictured: Aldebaran's Massive Die Revealed". Tom's Hardware. Retrieved 2022-11-20.
  11. ^ "Hot Chips 34 – AMD's Instinct MI200 Architecture". Chips and Cheese. 2022-09-18. Retrieved 2022-11-10.
  12. ^ "INTRODUCING AMD CDNA™ 2 ARCHITECTURE". AMD.com. Retrieved November 20, 2022.
  13. ^ Lam, Chester (Jul 28, 2023). "AMD’s Radeon Instinct MI210: GCN Lives On". Chips and Cheese. Retrieved 2 October 2025.
  14. ^ ""AMD Instinct MI200" Instruction Set Architecture". developer.amd.com. 2022-02-04. Retrieved 2022-10-11.
  15. ^ Smith, Ryan. "AMD Releases Instinct MI210 Accelerator: CDNA 2 On a PCIe Card". www.anandtech.com. Archived from the original on March 7, 2024. Retrieved 2024-06-03.
  16. ^ Smith, Ryan. "AMD Announces Instinct MI200 Accelerator Family: Taking Servers to Exascale and Beyond". www.anandtech.com. Archived from the original on November 8, 2021. Retrieved 2024-06-03.
  17. ^ Smith, Ryan. "CES 2023: AMD Instinct MI300 Data Center APU Silicon In Hand - 146B Transistors, Shipping H2'23". www.anandtech.com. Archived from the original on January 5, 2023. Retrieved 2023-01-22.
  18. ^ Paul Alcorn (2023-01-05). "AMD Instinct MI300 Data Center APU Pictured Up Close: 13 Chiplets, 146 Billion Transistors". Tom's Hardware. Retrieved 2023-01-22.
  19. ^ Kennedy, Patrick (2023-12-06). "AMD Instinct MI300X GPU and MI300A APUs Launched for AI Era". ServeTheHome. Retrieved 2024-04-15.
  20. ^ Lam, Chester. "Inside the AMD Instinct MI300A's Giant Memory Subsystem". chipsandcheese.com. Retrieved 2 October 2025.
  21. ^ Bonshor, Ryan Smith, Gavin. "The AMD Advancing AI & Instinct MI300 Launch Live Blog (Starts at 10am PT/18:00 UTC)". www.anandtech.com. Archived from the original on December 7, 2023. Retrieved 2024-06-03.
  22. ^ Smith, Ryan. "AMD Plans Massive Memory Instinct MI325X for Q4'24, Lays Out Accelerator Roadmap to 2026". www.anandtech.com. Archived from the original on June 3, 2024. Retrieved 2024-06-03.
  23. ^ "Advancing AI 2025 Keynote". AMD
  24. ^ "AMD Instinct™ MI350 Series GPUs". amd.com