{{Short description|Semiconductor manufacturing node}} {{use dmy dates|date=March 2022}} {{Semiconductor manufacturing processes}} The '''"32 nm" node''' is the step following the "45 nm" process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level.

Toshiba produced commercial 32{{nbsp}}GiB NAND flash memory chips with the "32{{nbsp}}nm" process in 2009.<ref name="toshiba2009">{{cite news |title=Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology |url=http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm |access-date=21 June 2019 |work=Toshiba |date=11 February 2009}}</ref> Intel and AMD produced commercial microchips using the "32 nm" process in the early 2010s. IBM and the Common Platform also developed a "32&nbsp;nm" high-κ metal gate process.<ref>Intel (Architecture & Silicon). [http://www.intel.com/content/www/us/en/silicon-innovations/gate-dielectric-scaling-for-cmos-guide.html Gate Dielectric Scaling for CMOS: from SiO<sub>2</sub>/PolySi to High-K/Metal-Gate]. White Paper. Intel.com. Retrieved 18 June 2013.</ref> Intel began selling its first "32&nbsp;nm" processors using the Westmere architecture on 7 January 2010.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=23 July 2020 |format= }}</ref> neither gate length, nor metal pitch, nor gate pitch on a "32nm" device is thirty-two nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=ExtremeTech}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref><ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref>

The "28 nm" node is an intermediate half-node die shrink based on the "32 nm" process.

The "32&nbsp;nm" process was superseded by commercial "22 nm" technology in 2012.<ref name=22nmIsHere>[http://www.tomshardware.com/news/intel-ivy-bridge-22nm-cpu-3d-transistor,14093.html "Report: Intel Scheduling 22 nm Ivy Bridge for April 2012"]. Tom'sHardware.com. 26 November 2011. Retrieved 5 December 2011.</ref><ref>[https://www.bbc.co.uk/news/technology-17785464 "Intel's Ivy Bridge chips launch using '3D transistors'"]. BBC. 23 April 2012. Retrieved 18 June 2013.</ref>

==Technology demos== Prototypes using "32&nbsp;nm" technology first emerged in the mid-2000s. In 2004, IBM demonstrated a 0.143&nbsp;μm<sup>2</sup> SRAM cell with a poly gate pitch of 135&nbsp;nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale.<ref>D. M. Fried et al., IEDM 2004.</ref> In October 2006, the Interuniversity Microelectronics Centre (IMEC) demonstrated a 32&nbsp;nm flash patterning capability based on double patterning and immersion lithography.<ref>[http://www.physorg.com/news80410095.html "IMEC demonstrates feasibility of double patterning immersion litho for 32nm node"]. PhysOrg.com. 18 October 2006. Retrieved 17 December 2011.</ref> The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45&nbsp;nm node.<ref>{{Cite news |title= IBM sees immersion at 22nm, pushes out EUV |author= Mark LaPedus |work= EE Times |date= 23 February 2007 |url= http://www.eetimes.com/electronics-news/4069824/IBM-sees-immersion-at-22nm-pushes-out-EUV/ |access-date=11 November 2011}}</ref> TSMC similarly used double patterning combined with immersion lithography to produce a "32&nbsp;nm" node 0.183&nbsp;μm<sup>2</sup> six-transistor SRAM cell in 2005.<ref>H-Y. Chen et al., Symp. on VLSI Tech. 2005.</ref>

Intel Corporation revealed its first "32&nbsp;nm" test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182&nbsp;μm<sup>2</sup>, used a second-generation high-κ gate dielectric and metal gate, and contained almost two billion transistors. 193&nbsp;nm immersion lithography was used for the critical layers, while 193&nbsp;nm or 248&nbsp;nm dry lithography was used on less critical layers. The critical pitch was 112.5&nbsp;nm.<ref>F. T. Chen (2002). <!-- title? -->''Proc. SPIE''. Vol. 4889, no. 1313.</ref>

In January 2011, Samsung completed development of the industry's first DDR4 SDRAM module using a process technology with a size between 30&nbsp;nm and 39&nbsp;nm. The module could reportedly achieve data transfer rates of 2.133&nbsp;Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent "30&nbsp;nm-class" process technology with speeds of up to 1.6&nbsp;Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 SDRAM to consume just half the current of DDR3 when reading and writing data.<ref>{{Cite news |title= Samsung trials DDR4 DRAM module |author= Peter Clarke |work= EE Times |date=4 January 2011 |url= http://www.eetimes.com/electronics-news/4211854/Samsung-trials-DDR4-DRAM-module/ |access-date=11 November 2011}}</ref>

==Processors using "32 nm" technology== Intel's Core i3 and i5 processors, released in January 2010, were among the first mass-produced processors to use "32&nbsp;nm" technology.<ref>[http://www.informationweek.com/news/security/management/showArticle.jhtml?articleID=222200708 "Intel Debuts 32-NM Westmere Desktop Processors"] {{Webarchive|url=https://web.archive.org/web/20100317232620/http://www.informationweek.com/news/security/management/showArticle.jhtml?articleID=222200708 |date=2010-03-17 }}. ''InformationWeek''. 7 January 2010. Retrieved 17 December 2011.</ref> Intel's second-generation Core processors, codenamed Sandy Bridge, also used the "32&nbsp;nm" manufacturing process. Intel's 6-core processor, codenamed Gulftown and built on the Westmere architecture, was released on 16 March 2010 as the Core i7 980x Extreme Edition, retailing for approximately US$1,000.<ref>{{Cite web |title= Intel's 6-core 32nm processors arriving soon |author= Sal Cangeloso |date= 4 February 2010 |publisher= Geek.com |url= http://www.geek.com/articles/chips/intels-6-core-32nm-processors-arriving-soon-2010024/ |access-date= 11 November 2011 |archive-date= 30 March 2012 |archive-url= https://web.archive.org/web/20120330104041/http://www.geek.com/articles/chips/intels-6-core-32nm-processors-arriving-soon-2010024/ |url-status= dead }}</ref> Intel's lower-end 6-core, the i7-970, was released in late July 2010, priced at approximately US$900. Intel's "32nm" process has a transistor density of 7.11 million transistors per square millimeter (MTr/mm2).<ref>{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | archive-url=https://web.archive.org/web/20190130194809/https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | url-status=dead | archive-date=30 January 2019 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }}</ref>

AMD also released "32&nbsp;nm" SOI processors in the early 2010s. AMD's FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology utilised a "32&nbsp;nm" SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design.

In September 2011, Ambarella Inc. announced the availability of the "32&nbsp;nm"-based A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities.<ref>{{Cite news |title= Ambarella A7L Enables the Next Generation of Digital Still Cameras with 1080p60 Fluid Motion Video |date= 26 September 2011 |publisher= Ambarella.com |url= http://www.ambarella.com/news/26/74/Ambarella-A7L-Enables-the-Next-Generation-of-Digital-Still-Cameras-with-1080p60-Fluid-Motion-Video.html |access-date= 11 November 2011 |archive-url= https://web.archive.org/web/20111110054035/http://www.ambarella.com/news/26/74/Ambarella-A7L-Enables-the-Next-Generation-of-Digital-Still-Cameras-with-1080p60-Fluid-Motion-Video.html |archive-date= 10 November 2011 |url-status= dead }}</ref>

==Successor node== ===28 nm & 22 nm=== The successor to "32&nbsp;nm" technology was the "22&nbsp;nm" node, per the International Technology Roadmap for Semiconductors. Intel began mass production of "22&nbsp;nm" semiconductors in late 2011,<ref>[http://seekingalpha.com/article/300442-intel-s-ceo-discusses-q3-2011-results-earnings-call-transcript "Intel's CEO Discusses Q3 2011 Results - Earnings Call Transcript"]. Seeking Alpha. 18 October 2011. Retrieved 14 February 2013.</ref> and announced the release of its first commercial "22&nbsp;nm" devices in April 2012.<ref name=22nmIsHere/><ref>[https://www.bbc.co.uk/news/business-17750330 "Intel beats analysts' first quarter forecasts"]. BBC. 17 April 2012. Retrieved 18 June 2013.</ref> TSMC bypassed "32{{nbsp}}nm", jumping from "40{{nbsp}}nm" in 2008 to "28{{nbsp}}nm" in 2011.<ref>{{cite web |title=28nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/28nm.htm |publisher=TSMC |access-date=30 June 2019}}</ref>

==References== {{Reflist|30em}}

==Further reading== *{{cite journal |first=S. |last=Steen |title=Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes |journal= Microelectronic Engineering|volume=83 |issue=4–9 |pages=754–761 |year=2006 |doi=10.1016/j.mee.2006.01.181 |display-authors=etal}}

==External links== *[http://news.cnet.com/Chipmakers+gear+up+for+manufacturing+hurdles/2100-1006_3-6082393.html Chipmakers gear up for manufacturing hurdles] *[http://www.sony.net/SonyInfo/News/Press/200601/06-0112E/ Sony, IBM, and Toshiba partnering on semiconductor research] *[http://www.pcworld.com/news/article/0,aid,117889,00.asp IBM and AMD partnering on semiconductor research] {{Webarchive|url=https://web.archive.org/web/20060716191735/http://www.pcworld.com/news/article/0,aid,117889,00.asp |date=2006-07-16 }} *[http://hardware.slashdot.org/comments.pl?sid=189944&cid=15632847 Slashdot discussion] *[http://www.physorg.com/news109344893.html Intel 32&nbsp;nm process] *[http://sst.pennnet.com/display_article/309943/5/ARTCL/none/none/1/Samsung-touts-30&nbsp;nm-NAND-flash-using-double-patterning/ Samsung self-aligned double patterning technology]{{Dead link|date=March 2021 |bot=InternetArchiveBot |fix-attempted=yes }}

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