{{Short description|Family of RISC microprocessors and microcontrollers}} {{Redirect|29K|the Soviet self-propelled anti-aircraft weapon|29K (artillery)}} thumb|AMD 29000 microprocessor right|thumb|AMD 29030 The '''AMD Am29000''', commonly shortened to '''29k''', is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant improvements. They were commonly used in laser printers from several manufacturers of the era and well documented as being used in the high-end HP Color LaserJet series from the first model Color LaserJet (Am29030) up to and including the HP Color LaserJet 5 which uses a Am29040.
Developed since 1984–1985, announced in March 1987 and released in May 1988,<ref>{{cite magazine |last1=Martin |first1=James A. |title=Firm says 32-bit chip handles 17 MIPS |url=https://books.google.com/books?id=jDYGHejAySsC&pg=PA14 |magazine=Computerworld |volume=21 |issue=12 |date=23 March 1987 |page=14}}</ref><ref>{{cite magazine |last1=Cole |first1=Bernard C. |title=RISC Slugfest: Is Marketing More Important Than Performance? |magazine=Electronics |url=https://worldradiohistory.com/Archive-Electronics/80s/88/Electronics-1988-04-28.pdf |page=66 (p. 68 of .pdf) |date=28 April 1988}}</ref><ref name="Johnson">{{cite interview |title=Oral History of William Michael 'Mike' Johnson |url=http://archive.computerhistory.org/resources/access/text/2014/10/102739914-05-01-acc.pdf |interviewer=Kevin Krewell |website=Computer History Museum |date=9 May 2014 |quote=Well, it started in '85. And it took I would say about three years and maybe four revs till it was functional.}}</ref> the initial Am29000 was followed by several versions, ending with the Am29040 in 1995.<ref>{{cite journal |last1=Betker |first1=Michael R. |last2=Fernando |first2=John S. |last3=Whalen |first3=Shaun P. |title=The History of the Microprocessor |journal=Bell Labs Technical Journal |date=Autumn 1997 |page=48 |url=https://www.bellsystemmemorial.com/pdf/bell_labs_journals/bell_labs_technical_journal_autumn_1997_3.pdf}}</ref> The 29050 was notable for being early to feature a floating point unit capable of executing one multiply–add operation per cycle.
AMD was designing a superscalar version until late 1995, when AMD dropped the development of the 29k because the design team was transferred to support the PC (x86) side of the business. What remained of AMD's embedded business was realigned towards the embedded 186 family of 80186 derivatives. By then the majority of AMD's resources were concentrated on their high-performance x86 processors for desktop PCs, using many of the ideas and individual parts of the 29k designs to produce the AMD K5.
==Design== The 29k evolved from the same Berkeley RISC design that also led to the Sun SPARC, Intel i960, ARM and RISC-V.
One design element used in some of the Berkeley RISC-derived designs is the concept of register windows, a technique used to speed up procedure calls significantly. The idea is to use a large set of registers as a stack, loading local data into a set of registers during a call, and marking them "dead" when the procedure returns. Values being returned from the routines would be placed in the "global page", the top eight registers in the SPARC (for instance). The competing early RISC design from Stanford University, the Stanford MIPS, also looked at this concept but decided that improved compilers could make more efficient use of general purpose registers than a hard-wired window.
In the original Berkeley design, SPARC, and i960, the windows were fixed in size. A routine using only one local variable would still use up eight registers on the SPARC, wasting this expensive resource. It was here that the 29k differed from these earlier designs, using a variable window size. In this example only two registers would be used, one for the local variable, another for the return address. It also added more registers, including the same 128 registers for the procedure stack, but adding another 64 for global access. In comparison, the SPARC had 128 registers in total, and the global set was a standard window of eight. This change resulted in much better register use in the 29000 under a wide variety of workloads.
The 29k also extended the register window stack with an in-memory (and in theory, in-cache) stack. When the window filled the calls would be pushed off the end of the register stack into memory, restored as required when the routine returned. Generally, the 29k's register usage was considerably more advanced than competing designs based on the Berkeley concepts.
thumb|AMD 29040
Another difference from the Berkeley design is that the 29k avoided use of the condition codes. Although the 29k generates the standard NZVC flags after arithmetic and logical operations, their only ''use'' was by the add and subtract with carry instructions. Conditional branches were limited to branching on the most significant (sign) bit of a general-purpose register, which could be set by one of a series of compare instructions (such as "signed greater than" or "equal") Any register could be used for this purpose, allowing the conditions to be easily saved at the expense of complicating some code. A Branch Target Cache (512 bytes on the 29000 and 1024 bytes on the 29050) stored sets of 4 or 2 sequential instructions found at the branch target address, reducing the instruction fetch latency during taken branches—the 29000 did not include any branch prediction system so there was a delay if a branch was taken. It means the 29000 has a single branch delay slot.<ref>{{Cite web |url=https://ia902802.us.archive.org/22/items/29kprog/29kprog.pdf#page=78 |title=Evaluating and Programming the 29K RISC Family Third Edition – DRAFT |page=54 |accessdate=2023-12-20}}</ref> The buffer mitigated this by storing four or two instructions from the target address of the branch, which could be run instantly while the fetch buffer was re-filled with new instructions from memory.<ref name="stewart1990">{{cite conference |first=Brett |last=Stewart |title=New generations of the 29 K family solutions |book-title=Digest of Papers Compcon Spring '90 |conference=Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage| year=1990 |pages=295–298 |doi=10.1109/CMPCON.1990.63690}}</ref>
Support for virtual address translation followed a similar approach to that of the MIPS architecture. A 64-entry translation lookaside buffer (TLB) retained mappings from virtual to physical addresses, and upon an untranslated address being encountered, the resulting TLB "miss" would cause the processor to trap to a software routine responsible for providing any appropriate mapping to physical memory. In contrast to the MIPS approach which employed a ''random'' register to select the TLB entry to be replaced upon a TLB miss event, the 29000 provided a dedicated ''lru'' (least recently used) register.<ref name="ieeemicro199202_mann">{{ cite magazine | url=https://archive.org/details/ieee_micro_v11n5_oct_91/page/n204/mode/1up | title=Unix and the Am29000 Microprocessor | magazine=IEEE Micro | issn=0272-1732 | last1=Mann | first1=Daniel | date=October 1991 | access-date=19 May 2023 | pages=23–31 }}</ref> Some products in the 29000 family provided only 16 TLB entries to be able to dedicate part of the silicon to peripherals. To compensate, the maximum page size employed by a mapping was increased from 8 KB to 16 MB.<ref name="mann1995">{{ cite book | url=https://archive.org/details/29kprog/mode/2up | title=Evaluating and Programming the 29K RISC Family | publisher=Advanced Micro Devices | last1=Mann | first1=Daniel | date=1995 | access-date=19 May 2023 }}</ref>{{rp|pages=305–306}}
==Versions== The first Am29000 was released in 1988, including a built-in MMU but floating point support was offloaded to the '''Am29027''' FPU. Units with failed MMU or Branch Target Cache were sold as the '''Am29005'''.{{r|stewart1990}}
In 1991 the line was extended with the '''Am29030''' and '''Am29035''', which included an 8 KB or 4 KB of instruction cache, respectively.<ref>{{cite magazine |last1=Fickel |first1=Louise |title=Advanced Micro Devices Bolsters 29000 Family With Two RISC CPUs |url=https://books.google.com/books?id=WVAEAAAAMBAJ&pg=PT27 |magazine=InfoWorld |volume=13 |issue=19 |page=28 |date=13 May 1991}}</ref> By then<ref>{{cite web |title=FLASH MEMORY ANNOUNCEMENTS |url=https://techmonitor.ai/technology/flash_memory_announcements |website=Computer Business Review archive at Tech Monitor |date=9 October 1990}}</ref> the '''Am29050''' had also become available, without on-chip cache but featuring a floating-point unit with fully pipelined multiply–accumulate operations, a larger 1 KB Branch Target Cache with a claimed 80% hit rate, and better-pipelined load operations sped up by a 4-entry TLB-like Physical Address Cache. Though it is not a superscalar processor, it permits a floating-point operation and an integer operation to complete at the same cycle. The integer and floating-point sides each have an own write port to the registers.<ref name="manual">{{cite web |title=Am29050 Microprocessor User's Manual |url=https://archive.org/details/bitsavers_amddataBooManual_30055159/mode/2up |website=archive.org |date=1991}}</ref> It contained 428,000 transistors<ref>{{cite conference |last1=Ganapathy |first1=Gopi |last2=Abraham |first2=Jacob A. |title=Hardware Acceleration Alone Will Not Make Fault Grading ULSI A Reality |conference=International Test Conference 1991 |url=https://booksc.eu/ireader/29486624}}</ref> on a 1-micron process<ref>{{cite conference |last1=Lynch |first1=Thomas Walker |last2=Swartzlander (Jr) |first2=Earl E. |title=The redundant cell adder |book-title=Proceedings, 10th IEEE Symposium on Computer Arithmetic |date=July 1991 |doi=10.1109/ARITH.1991.145553 |url=https://www.researchgate.net/publication/3517557}}</ref> with a 0.8-micron effective channel length<ref name="manual"/> and was available at 20, 25, 33, and 40 MHz. Later the '''Am29040''' was released at 33, 40, and 50 MHz, being like the Am29030 except for featuring a 4 KB data cache, a multiplication unit, and a few other enhancements.<ref>{{cite web |title=Am29040 High-Performance RISC Microprocessor with Instruction and Data Caches |url=http://datasheets.chipdb.org/AMD/29K/040_ds.pdf |website=chipdb.org |access-date=18 September 2022}}</ref> The 119 mm<sup>2</sup> Am29040 contained 1.2 million transistors on a 0.7-micron process.<ref>{{cite journal |last1=Gwennap |first1=Linley |title=Digital, MIPS Add Multimedia Extensions |journal=Microprocessor Report |volume=10 |issue=15 |pages=24–28|url=https://www.ardent-tool.com/CPU/docs/MPR/1015.pdf}}</ref><ref>{{cite book |title=Microprocessor Forum folder |url=https://www.computerhistory.org/collections/catalog/102701945 |year=1994 }}</ref>
A superscalar version of 29K was being designed, but canceled in favor of x86. It was codenamed ''Jaguar'',<ref name="Johnson"/> and was described in November 1994 and August 1995.<ref name="hc">{{cite web |last1=McMinn |first1=Brian |title=The First Superscalar 29K Family Member |url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc07/2_Mon/HC7.S1/HC7.1.1.pdf |website=Hot Chips |date=14 August 1995}}</ref><ref>{{cite web |title=FIRST SUPERSCALAR Am29000 REVEALED |url=https://techmonitor.ai/technology/first_superscalar_am29000_revealed |website=Computer Business Review archive at Tech Monitor |date=28 November 1994}}</ref> It was an advanced design, capable of four-way dispatch into six reservation stations and speculative out-of-order execution of instructions, with four-way retire. The register file permitted four reads and two writes at once. The caches for instructions and data were 8 KB each. Loads from cache could bypass stores. It had no on-chip FPU due to cost reasons and the target market. It was expected to attain 100 MHz frequency on a 0.4-micron process.<ref name="hc"/><ref>{{cite news |last=Detar |first=Jim |date=31 October 1994 |title=AMD brews up Superscalar 29K |newspaper=Electronic News}}</ref>
AMD used the unreleased 29K microarchitecture as the basis of the K5 series of x86-compatible processors. The ALUs were carried over, as was the re-order buffer with a slight modification. The FPU was taken from the 29050, but extended to 80 bits precision. The K5 translated the x86 instructions into "RISC-OPs" upon decoding, aided by the predecode information held of the cached instructions. AMD claimed that the superscalar 29K would have only a slightly lower performance than the K5, but much lower cost due to the size difference.<ref>{{cite journal |last1=Slater |first1=Michael |title=AMD's K5 Designed to Outrun Pentium |journal=Microprocessor Report |volume=8 |issue=14 |pages=1–7 |url=http://cgiold.di.uoa.gr/~halatsis/Advanced_Comp_Arch/Papers/k5.pdf |date=24 October 1994}}</ref><ref name="hc"/>
The Honeywell 29KII is a CPU based on the AMD 29050, and it was extensively used in real-time avionics.
<gallery caption="Die photos" mode=packed heights=160px> Image:AMD_Am29000_die.JPG|Am29000 Image:AMD_Am29030_die.jpg|Am29030 Image:AMD_Am29040_die.JPG|Am29040 Image:AMD_Am29050_die.JPG|Am29050 </gallery>
==Products and applications== Positioned as a product for "medium- to high-performance embedded applications" with potential for use in Unix workstations,<ref name="ieeemicro199202_mann"/> the 29000 was used in a variety of products such as X terminals, laser printer controller cards, graphics accelerator cards, optical character recognition solutions, and network bridges.<ref name="fusionews29k_summer1990">{{ cite book | url=https://archive.org/details/TNM_FUSIONews_29K_Issues_3_Summer_1990_-_AMD_20170828_0001/mode/2up | title=FUSIONews 29K | publisher=Advanced Micro Devices | date=Summer 1990 | access-date=20 May 2023 | issue=3 }}</ref> The memory architecture of the 29000 was a particular attraction for product designers, allowing them to forego external cache memory and to employ dynamic RAM directly while maintaining acceptable performance,<ref name="fusionews29k_summer1990"/>{{rp|pages=1|quote=In addition, the 29K's memory interface allowed us to use a DRAM only memory architecture. In an X Terminal, the monitor and memory are the two biggest expenses. Samsung makes both!}} permitting a degree of flexibility in the choice of memory technologies used to retain program instructions and data.<ref name="byte198805_marshall">{{ cite magazine | url=https://archive.org/details/BYTE-1988-05/page/n286/mode/1up | title=Real-World RISCs | magazine=Byte | date=May 1988 | access-date=20 May 2023 | last1=Marshall | first1=Trevor | pages=263–268 }}</ref>
The 29k saw some use as a computational accelerator or coprocessor, particularly on the Macintosh and IBM PC-compatible platforms. For instance, Yarc Systems Corporation produced 29k-based "RISC coprocessor" cards for Macintosh II and PC AT systems, alongside other "CISC coprocessor" cards featuring Motorola 68020 and 68030 processors, and "parallel coprocessor" cards featuring T800 transputer processors.<ref name="yarc">{{ cite book | url=https://archive.org/details/TNM_YARC_coprocessors_for_PC_and_Macintosh_20170830_0134/mode/2up | title=YARC, the solutions company | publisher=Yarc Systems Corporation }}</ref> Its ''NuSuper'' (originally named the ''McCray''<ref name="byte198808_yarc">{{ cite magazine | url=https://archive.org/details/BYTE-1988-08/page/n19/mode/1up | title=YARC Claims 50-MHz Operation for Mac II Booster Board | magazine=Byte | date=August 1988 | access-date=20 May 2023 | pages=16 }}</ref>) and ''AT-Super'' cards, employing the Am29000 CPU and Am29027 floating-point accelerator,<ref name="yarc"/> were followed by the ''MacRageous'', upgrading the CPU to the Am29050.<ref name="macrageous">{{ cite book | url=https://archive.org/details/TNM_MacRageous_Macintosh-III_RISC_coprocessor_sys_20170827_0691/mode/2up | title=MacRageous Macintosh-II RISC Coprocessor System | date=1990 | publisher=Yarc Systems Corporation }}</ref> Such accelerator cards offered performance several times that of the Macintosh II itself and benchmarked competitively with RISC workstations such as the DECstation 3100. Multiple cards could also be fitted to a system. However, the cost of a Macintosh II system combined with such a card approached that of established RISC workstations running Unix.<ref name="mips198910_yarc">{{ cite magazine | url=https://archive.org/details/sim_personal-workstation_1989-10_1_10/page/n92/mode/1up | title=YARC's NuSuper Soups Up the Mac | magazine=MIPS | date=October 1989 | access-date=20 May 2023 | last1=Varhol | first1=Peter D. | pages=81–83 }}</ref> The AT-Super was priced at around $4,600 and was reported as running Unix, competing with similar products employing Intel's i860 processor.<ref name="computerworld19900903_yarc">{{ cite magazine | url=https://archive.org/details/computerworld2436unse/page/37/mode/1up | title=Mating Intel PCs with RISC | magazine=Computerworld | last1=Pastore | first1=Richard | date=3 September 1990 | access-date=3 March 2024 | pages=37 }}</ref>
One notable product utilising the 29k was Apple's ''Macintosh Display Card 8·24 GC'' for its Macintosh IIfx, featuring a 30 MHz Am29000 processor, 64 KB static RAM cache, and 2 MB of video RAM, with the option of an additional 2 MB of dynamic RAM for use by the QuickDraw graphical toolkit. The inclusion of the 29k differentiated this particular version of the card from other versions sold by Apple, significantly improving performance when handling 24-bits-per-pixel images.<ref name="personalworkstation199005_mac2fx">{{ cite magazine | url=https://archive.org/details/sim_personal-workstation_1990-05_2_5/page/46/mode/2up | title=A Big, Fast, Macintosh with RISC Graphics | magazine=Personal Workstation | last1=Smith | first1=Bud E. | date=May 1990 | access-date=20 May 2023 | pages=46–50 }}</ref>
==See also== *List of AMD Am2900 and Am29000 families
==References== {{Reflist}}
==External links== *[http://www.cpushack.com/Am29k.html AMD 29k (Streamlined Instruction Processor) ID Guide] *{{Citation |url=http://datasheets.chipdb.org/AMD/29K/29kprog.pdf |title=Evaluating and Programming the 29K RISC Family |archive-url=https://web.archive.org/web/20070927060927/http://www.amd.com/epd/29k/29kprog/29kprog.pdf |archive-date=September 27, 2007 |first=Daniel |last=Mann |year=1995 |publisher=Advanced Micro Devices}} pdf book about 29k family *[http://www.chipdb.org/cat-29000-974.htm chipdb.org] Images of different Am29000 processors
{{AMD processors}} {{RISC-based processor architectures}} {{Microcontrollers}} {{Authority control}}
Category:Microcontrollers Am29000 Category:Superscalar microprocessors Category:32-bit microprocessors Category:Computer-related introductions in 1988