# Z/Architecture

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This article is about z/Architecture mode. For z/Architecture in ESA/390 mode, see [ESA/390](/source/ESA/390).

**z/Architecture**, initially and briefly called **[ESA](/source/ESA/390) Modal Extensions** (**ESAME**), is [IBM](/source/IBM)'s [64-bit](/source/64-bit_computing) [complex instruction set computer](/source/Complex_instruction_set_computer) (CISC) [instruction set architecture](/source/Instruction_set_architecture), implemented by its [mainframe computers](/source/Mainframe_computer). IBM introduced its first z/Architecture-based system, the [z900](/source/IBM_System_z#IBM_zSeries_family), in late 2000.[1] Subsequent z/Architecture systems include the IBM z800, z990, z890, [System z9](/source/System_z9), [System z10](/source/IBM_System_z10), [zEnterprise 196](/source/ZEnterprise_196), [zEnterprise 114](/source/ZEnterprise_114), [zEC12](/source/IBM_Z#zEnterprise_gen2_(zBC12_and_zEC12)), [zBC12](/source/IBM_Z#zEnterprise_gen2_(zBC12_and_zEC12)), [z13](/source/IBM_Z#IBM_z13), [z14](/source/IBM_Z#IBM_z14), [z15](/source/IBM_Z#IBM_z15), [z16](/source/IBM_Z#IBM_z16), and [z17](/source/IBM_Z#IBM_z17).

z/Architecture retains [backward compatibility](/source/Backward_compatibility) with previous 32-bit-data/31-bit-addressing architecture [ESA/390](/source/ESA/390) and its predecessors back to the 32-bit-data/24-bit-addressing [System/360](/source/System/360). The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode.[2] However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.

## Features

z/Architecture includes almost all[a] of the features of [ESA/390](/source/ESA/390), and adds some new features. Among the features[b] of z/Architecture are

- A channel subsystem with the architecture introduced by [S/370-XA](/source/IBM_System/370-XA)
- Branch relative instructions introduced by ESA/390, with 16-bit signed halfword offsets
- Relative long instructions, with 32-bit signed halfword offsets
- Trimodal (24/31/64-bit) addresses
- 16 32-bit access registers (ARs) introduced by [ESA/370](/source/ESA/370)
- 16 64-bit general registers (GRs), 32-bit on older architectures
- 16 64-bit control registers (CRs) introduced by [System/370](/source/IBM_System/370) as 32-bit
- 16 64-bit floating-point registers (FPRs)
- 32 128-bit vector registers (VRs); bits 0–63 of VR0–VR15 contain FPR0–FPR15
- 1 32-bit floating-point control (FPC) register
- 1 128-bit program-status word[c] (PSW), which includes a 64-bit instruction address
- An 8-KiB prefix storage area (PSA)
- Cryptographic Facility
- [IEEE Binary-floating-point](/source/IEEE_754#Binary) instructions added by ESA/390
- [IEEE Decimal-floating-point](/source/IEEE_754#Decimal) instructions

For information on when each feature was introduced, consult the Principles of Operation.[3][4]

### Extended-immediate facility

The extended-immediate facility adds instructions with 32-bit signed and unsigned immediate operands, Find Leftmost ones, and miscellaneous load instructions, e.g., Load and test, Load byte, Load logical character.

### General-instructions-extension facility

The general-instructions-extension facility add 3 dozen instructions, including

- Compare and branch instructions
- Compare and trap instructions
- Load instructions, e.g. Load and test (LT)
- Store instructions

### High-word facility

The high-word facility provides instructions operating on the high word of a 64-bit general register.

### Long-displacement facility

The long-displacement facility adds instructions with a 20-bit signed displacement, e.g., LAY.

### Miscellaneous-instruction-extensions Facility 1

The miscellaneous-instruction-extensions Facility 1 adds

- Compare logical and trap (CLT and CLGT)
- Rotate then insert selected bits (RISBGN)

### Miscellaneous-instruction-extensions Facility 2

The miscellaneous-instruction-extensions Facility 2 adds

- Branch indirect on condition (BIC)
- new add, multiply and subtract instructions

### Miscellaneous-instruction-extensions Facility 3

The miscellaneous-instruction-extensions Facility 3

- And with complement (NCRK, NCGRK)
- Move right to left (MVCRL)
- Not and (NNRK, NNGRK)
- Not exclusive or (NXRK, NXGRK)
- Not or (NORK, NOGRK)
- Or with complement (OCRK, OCGRK)
- Select (SELR, SELGR)
- Select high (SELFHR)

### Vector facility

The [z13](/source/IBM_z13) introduced a 128-bit Packed [SIMD](/source/SIMD) facility named "Vector Facility",[d] which was first documented in edition 11 of z/Architecture Principles of Operation.[5] It adds 32 vector registers, each 128 bits wide; the existing 16 floating-point registers are overlaid on the new vector registers. The new architecture adds over 150 new instructions to operate on data in vector registers, including integer, floating-point, and string data types. The z13 implementation includes two independent [SIMD](/source/SIMD) units to operate on vector data.[6] The older [vector processor](/source/Vector_processor) facility first introduced from the [IBM 3090](/source/IBM_3090) and also supported in the [ES/9000](/source/ES/9000) is not supported in z/Architecture.[7]

### Neural-network-processing-assist facility

The [z16](/source/IBM_Telum) introduced the Neural-network-processing-assist facility,[8][9] which introduces several instructions performing operations on model-dependent data types. For the z16 this is the 16-bit NNP-Data-Type-1 Format.

The new instructions include tensor operations useful for AI and neural network applications.

## Registers

IBM z/Architecture registers General Registers 0–15 Two's complement value 0 31 Two's complement value (continued) 32 63 Access Registers 0–15[10] 0 0 0 0 0 0 0 P ALESN ALEN 0 6 7 8 15 16 31 z/Architecture Access register abbreviations Bits Field Meaning 0–6 0000000 7 P Primary 0=use dispatchable-unit access list 1=use primary-space access list 8–15 ALESN access-list-entry sequence number 16–31 ALEN access-list-entry number Breaking-event-address register (BEAR) See Principles of Operation[11] 0 31 (continued) 32 63 Control Registers 0–15 See Principles of Operation[12] or Control Registers 0 31 (continued) 32 63 Floating-Point Registers (hexadecimal) 0–15 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63 Floating-Point Registers (binary, single precision) 0–15 S Biased exponent Mantissa 0 1 8 9 31 Floating-Point Registers (binary, double precision) 0–15 S Biased exponent Mantissa 0 1 11 12 31 Mantissa (continued) 32 63 Prefix register[13] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Prefix Bits 33–50 0 n/a 32 33 50 51 52 63 z/Architecture long PSW[14] 0 R 0 style="border-style: solid none solid | 0 0 T I O E X Key 0 M W P AS CC Program Mask R I 0 style="border-style: solid none solid | 0 style="border-style: solid none solid | 0 style="border-style: solid none solid | 0 style="border-style: solid none solid | 0 0 E A 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 30 31 B A 0 32 33 63 Instruction Address 64 95 Instruction Address (Continued) 96 style="width:1%; text-align:right; border-style: none none none none;' | 127 Long PSW abbreviations Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O mask 7 EX External Mask 8–11 Key PSW key 12 E=0 Must be zero for LPSWE 13 M Machine-check mask 14 W Wait state 15 P Problem state 16–17 AS Address-Space Control 00=primary-space mode 01=Access-register mode 10=Secondary-space mode 11=Home-space mode 18–19 CC Condition Code 20–23 PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 HFP Exponent underflow 23 HFP Significance 24 RI Reserved for IBM 31 EA Extended Addressing mode 0=defined by BA below; 1=64-bit, BA must be zero 32 BA Basic Addressing mode 0=24 or 64; 1=31 64–127 IA Instruction Address z/Architecture short PSW[15] 0 R 0 style="border-style: solid none solid | 0 0 T I O E X Key 1 M W P AS CC Program Mask R I 0 0 0 0 0 0 E A 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 25 30 31 B A Instruction Address 32 33 63 Short PSW abbreviations Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O mask 7 EX External Mask 8–11 Key PSW key 12 E=1 Must be one for LPSW 13 M Machine-check mask 14 W Wait state 15 P Problem state 16–17 AS Address-Space Control 00=primary-space mode 01=Access-register mode 10=Secondary-space mode 11=Home-space mode 18–19 CC Condition Code 20–23 PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 HFP Exponent underflow 23 HFP Significance 24 RI Reserved for IBM 31 EA Extended Addressing mode 0=defined by BA below; 1=64-bit, BA must be zero 32 BA Basic Addressing mode 0=24 or 64; 1=31 33–63 IA Instruction Address

Each processor has these registers

- [Access registers](#Access_registers)
- [Breaking-event-address register (BEAR)](#breaking-event-address_register_(BEAR))
- [Control registers](#Control_registers)
- [Floating-point Control (FPC) register](#Floating-point_Control_(FPC)_register)
- [Floating-point registers](#Floating-point_registers)
- [General registers](#General_registers)
- [Prefix register](#Prefix_register)
- [Program status word (PSW)](#Program_status_word_(PSW))
- [Vector registers](#Vector_registers)

### Access registers

Each CPU has 16 32-bit access registers.[10][16] When a program running in AR mode specifies register 1–15 as a base register or as a register operand containing an address, the CPU uses the associated access register during address translation.

### Breaking-event-address register (BEAR)

The 64-bit BEAR[11][17] contains the address of the last instruction that broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 (). After an Execute of a branch, the BEAR contains the address of the execute, not that of the branch.

### Control registers

The 16 64-bit control registers provide controls over and the status of a CPU, except for information included in the PSW. They are an evolutionary enhancement to the control registers on the earlier [ESA/390](/source/ESA/390) on the [IBM S/390](/source/IBM_S/390) processors. For details on which fields are dependent on specific features, consult the Principles of Operation.[18] Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

z/Architecture mode control registers CR bits Field 0 8 Transactional-execution control 0 9 Transactional-execution program-interruption filtering override 0 10 Clock-comparator sign control 0 13 Cryptography counter control 0 14 Processor-activity-instrumentation-extension control 0 15 Measurement-counter-extraction-authorization control 0 30 Warning-track subclass mask 0 32 TRACE TOD-clock control 0 33 SSM-suppression 0 34 TOD-clock-sync control 0 35 Low-address-protection control 0 36 Extraction-authority control 0 37 Secondary-space control 0 38 Fetch-protection-override control 0 39 Storage-protection-override control 0 40 Enhanced-DAT-enablement control 0 43 Instruction-execution-protection-enablement control 0 44 ASN-and-LX-reuse control 0 45 AFP-register control 0 46 Vector enablement control 0 48 Malfunction-alert subclass mask 0 48 Malfunction-alert subclass mask 0 49 Emergency-signal subclass mask 0 50 External-call subclass mask 0 52 Clock-comparator subclass mask 0 53 CPU-timer subclass mask 0 54 Service-signal subclass mask 0 56 Initialized to 1 0 57 Interrupt-key subclass mask 0 58 Measurement-alert subclass mask 0 59 Timing-alert subclass mask 0 61 Crypto control 1 0–51 Primary Address-Space Control Element (ASCE) Primary region-table origin Primary segment-table origin Primary real-space token origin 1 54 Primary subspace-group control 1 55 Primary private-space control 1 56 Primary storage-alteration-event 1 57 Primary space-switch-event control 1 58 Primary real-space control 1 60–61 Primary designation-type control 1 62–63 Primary table length 2 33–57 Dispatchable-unit-control-table origin 2 59 Guarded-storage-facility enablement control 2 61 Transaction diagnostic scope 2 62–63 Transaction diagnostic control 3 0–31 Secondary ASN-second-table-entry instance number 3 32–47 PSW-key mask 3 48–63 Secondary ASN 4 0–31 Primary ASN-second-table-entry instance number 4 32–47 Authorization index 4 48–63 Primary ASN 5 33–57 Primary-ASN-second-table-entry origin 6 32–39 I/O-interruption subclass mask 7 0–51 Secondary Address-Space Control Element (ASCE) Secondary region-table origin Secondary segment-table origin Secondary real-space token origin 7 54 Secondary subspace-group control 7 55 Secondary private-space control 7 56 Secondary storage-alteration-event control 7 58 Secondary real-space control 7 60–61 Secondary designation-type control 7 62–63 Secondary table length 8 16–31 Enhanced-monitor masks 8 32–47 Extended authorization index 8 48–63 Monitor masks 9 32 Successful-branching-event mask 9 33 Instruction-fetching-event mask 9 34 Storage-alteration-event mask 9 35 Storage-key-alteration-event mask 9 36 Store-using-real-address-event mask 9 37 Zero-address-detection-event mask 9 38 Transaction-end event mask 9 39 Instruction-fetching-nullification-event mask 9 40 Branch-address control 9 41 PER-event-suppression control 9 43 Storage-alteration-space control 10 0–63 PER starting address 11 0–63 PER ending address 12 0 Branch-trace control 12 1 Mode-trace control 12 2–61 Trace-entry address 12 62 ASN-trace control 12 63 Explicit-trace control 13 0–51 Home Address-Space Control Element (ASCE) Home region-table origin Home segment-table origin Home real-space token origin 13 55 Home private-space control 13 56 Home storage-alteration-eventl 13 57 Home space-switch-event control 13 58 Secondary real-space control 13 60–61 Home designation-type control 13 62–63 Home table length 14 32 Set to 1 14 33 Set to 1 14 34 Extended save-area control (ESA/390-compatibility mode only) 14 35 Channel-report-pending subclass mask 14 36 Recovery subclass mask 14 37 Degradation subclass mask 14 38 External-damage subclass mask 14 39 Warning subclass mask 14 42 TOD-clock-control-override control 14 44 ASN-translation control 14 45–63 ASN-first-table origin 15 0–60 Linkage-stack-entry address

### Floating-point Control (FPC) register

The FPC register contains Interrupt Masks (IM), Status Flags (SF), Data Exception Code (DXC), Decimal Rounding Mode (DRM) and Binary Rounding Mode (BRM). An interruption only stores the DXC if the FPC register if the AFP-register (additional floating-point register) control bit, bit 13 of control register 0, is one. Also, while individual bits of the DXC usually have significance, programs should normally treat it as an 8-bit integer rather than querying individual bits.

FPC fields Byte name Bits Field name Use masks 0 IMi IEEE-invalid-operation mask masks 1 IMz IEEE-division-by-zero mask masks 2 IMo IEEE-overflow mask masks 3 IMu IEEE-underflow mask masks 4 IMx IEEE-inexact mask masks 5 IMq Quantum-exception mask flags 8 SFi IEEE-invalid-operation flag flags 9 SFz IEEE-division-by-zero flags 10 SFo IEEE-overflow flag flags 11 SFu IEEE-underflow flag flags 12 SFx IEEE-inexact flag flags 13 SFq Quantum-exception flag DXC 16–23 DXC Data-exception code DXC 16 i IEEE-invalid-operation DXC 17 z IEEE-division-by-zero DXC 18 o IEEE-overflow DXC 19 u IEEE-underflow mask DXC 20 x IEEE-inexact mask DXC 21 y/q Quantum-exception mask 25–27 DRM DFP rounding mode 29–31 BRM BFP rounding mode

### Floating-point registers

Each CPU had 16 64-bit floating-point registers; FP0–15 occupy bits 0–63 of VR0–15. Ignoring the vector registers, floating point data may be in one of three formats and are in one of three sizes. z/Architecture supports

- [Hexadecimal floating point](/source/Hexadecimal_floating_point), a format inherited from [System/360](/source/System/360) - **E** - Single precision, in half of a FP register **D** - Double precision, a full FP register **X** - Extended precision in an even-odd pair of FP registers
- [IEEE 754](/source/IEEE_754) binary floating point - **E** - [Single precision](/source/Single-precision_floating-point_format), in half of a FP register **D** - [Double precision](/source/Double-precision_floating-point_format), in a full FP register **X** - [Extended precision](/source/Quadruple-precision_floating-point_format) in an even-odd pair of FP registers
- [IEEE 754](/source/IEEE_754) decimal floating point - **D** - [Double precision](/source/Decimal64_floating-point_format), in a full FP register **X** - [Extended precision](/source/Decimal128_floating-point_format) in an even-odd pair of FP registers

### General registers

Each CPU has 16 64-bit general registers, which serve as [accumulators](/source/Accumulator_(computing)), base registers[e] and [index registers](/source/Index_register).[e] Instructions designated as *Grandé* operate on all 64 bits; some instructions added by the Extended-Immediate Facility operate on any halfword or word in the register; most other instructions do not change or use bits 0–31.

### Prefix register

The prefix register is used in translating a real address to an absolute address. In z/Architecture mode, the PSA is 2 pages (8 KiB). Bits 0–32 and 51–63 are always zero. If bits 0–50 of a real address are zero then they are replaced by bits 0–50 of the prefix register; if bits 0–50 of the real address are equal to bits 0–50 of the prefix register then they are replaced with zeros.

### Program status word (PSW)

The PSW holds the instruction address and other fields reflecting the status of the program currently running on a CPU. The status of the program is also affected by the contents of the [Control registers](#Control_registers).

### Vector registers

Each CPU has 32 128-bit vector registers;[19] bits 0–63 of VR0–15 are also FPR0–15. A vector register may contain 16 8-bit fields, 8 16-bit fields, 4 32-bit fields, 2 64-bit fields or 1 128-bit field.

## Memory

IBM classifies memory in z/Architecture into **Main Storage** and **Expanded Storage**.

Main storage is addressed in 8-bit [bytes](/source/Bytes) ([octets](/source/Octet_(computing))), with larger aligned[f] groupings:

**Halfword**- Two bytes
- 16 bits
**Word**- Four bytes
- 32 bits
**Doubleword**- 8 bytes
- 64 bits
**Quadword**- 16 bytes
- 128 bits
**Page**- 4096 bytes

Although z/Architecture allows real and virtual addresses from 0 to 264-1, engineering constraints limit current and planned models to far less.

Expanded storage is addressed in 4 KiB blocks, with block numbers ranging from 0 to 232.

## Addressing

### Types of main storage addresses

There are three types of main storage addresses in z/Architecture

**Virtual address**- The address as seen by application programs. It is an offset into an address space and is subject to address translation via page and segment tables.
**Real address**- The address after address translation, or the address seen by an OS component running with translation off. It is subject to prefixing.
**Absolute address**- The address after prefixing references to the first two pages[g] via the prefix register.

### Address encoding

z/Architecture uses the same truncated addressing as ESA, with some additional instruction formats. As with ESA, in AR mode each nonzero base register is associated with a base register specifying the address space. Depending on the instruction, an address may be provided in several different formats.

**R**- The address is contained in a general register
**Relative**- A signed 16-bit halfword offset from the current instruction.
**Relative long**- A signed 32-bit halfword offset from the current instruction.
**RS**- A base register and a 12-bit displacement
**RSY**- A base register and a 20-bit displacement; formally known as long displacement, colloquially known as "Yonder".
**RX**- A base register, an index register, and a 12-bit displacement
**RXY**- A base register, an index register, and a 20-bit displacement; formally known as long displacement, colloquially known as "Yonder".
**SIY**- A base register, and a 20-bit displacement; formally known as long displacement, colloquially known as "Yonder".

### Addressing modes

In addition to the two addressing modes supported by [S/370-XA](/source/S/370-XA) and [ESA](/source/IBM_Enterprise_Systems_Architecture), a/Architecture has an extended addressing mode with 64-bit virtual addresses. The addressing mode is controlled by the EA (bit 31) and BA (bit 32) bits in the PSW. The valid combinations are

- 00 24-bit addressing
- 01 31-bit addressing
- 11 64-bit addressing

### Translation modes

z/Architecture supports four virtual *translation modes*, controlled by[20] bit 5, the DAT-mode bit, and bits 16–17, the Address-Space Control (AS) bits, of the [PSW](#Program_status_word_(PSW)).

**Primary-space mode**- All storage references use the translation tables for the primary address space
**Access-register mode**- All storage references use the translation tables designated by the access register associated with the base register.
**Secondary-space mode**- All storage references use the translation tables for the secondary address space
**Home-space mode**- All storage references use the translation tables for the home address space

## Operating system support

IBM's [operating systems](/source/Operating_system) [z/OS](/source/Z/OS), [z/VSE](/source/Z/VSE), [z/TPF](/source/Z/TPF), and [z/VM](/source/Z/VM) are versions of [MVS](/source/MVS), [VSE](/source/VSE_(operating_system)), [Transaction Processing Facility](/source/Transaction_Processing_Facility) (TPF), and [VM](/source/VM_(operating_system)) that support z/Architecture. Older versions of z/OS, z/VSE, and z/VM continued to support 32-bit systems; z/OS version 1.6 and later, z/VSE Version 4 and later, and [z/VM](/source/Z/VM) Version 5 and later require z/Architecture.

[Linux](/source/Linux) also supports z/Architecture with [Linux on IBM Z](/source/Linux_on_IBM_Z).

z/Architecture supports running multiple concurrent operating systems and applications even if they use different address sizes. This allows software developers to choose the address size that is most advantageous for their applications and data structures.

On July 7, 2009, IBM on occasion of announcing a new version of one of its operating systems implicitly stated that **Architecture Level Set 4** (**ALS 4**) exists, and is implemented on the System z10 and subsequent machines.[21][22] The ALS 4 is also specified in LOADxx as **ARCHLVL 3**, whereas the earlier z900, z800, z990, z890, System z9 specified ARCHLVL 2. Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating-point unit (HDFU).[23][24]

Most[citation needed] [operating systems](/source/Operating_system) for the z/Architecture, including [z/OS](/source/Z/OS), generally restrict code execution to the first 2 GB (31 address bits, or 231 addressable bytes) of each [virtual address space](/source/Virtual_address_space) for reasons of efficiency and compatibility rather than because of architectural limits. Linux on IBM Z allows code to execute within 64-bit address ranges.

### z/OS

Each z/OS [address space](/source/Memory_address), called a 64-bit address space, is 16 [exabytes](/source/Exabyte) in size.

#### Code (or mixed) spaces

The z/OS implementation of the [Java programming language](/source/Java_programming_language) is an exception.[how?] The z/OS [virtual memory](/source/Virtual_memory) implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code.

#### Data-only spaces

Data-only spaces are memory regions that can be read from and written to, but not used as executable code. (Similar to the [NX bit](/source/NX_bit) on other modern processors.) By default, the z/Architecture memory space is indexed by 64-bit pointers, allowing up to 16 exabytes of memory to be visible to an executing program.

#### Dataspaces and hiperspaces

Applications that need more than a 16 [exabyte](/source/Exabyte) data address space can employ extended [addressability](/source/Computer_data_storage) techniques, using additional address spaces or data-only spaces. The data-only spaces that are available for user programs are called:

- **dataspaces** (sometimes referred to as "data spaces")[25][26] and
- **hiperspaces** (High performance space).[27][28]

These spaces are similar in that both are areas of virtual storage that a program can create, and can be up to 2 [gigabytes](/source/Gigabyte). Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas. Program code cannot run in a dataspace or a hiperspace.[29]

A dataspace differs from a hiperspace in that dataspaces are byte-addressable, whereas hiperspaces are page-addressable.

### IBM mainframe expanded storage

Traditionally, memory has been [byte-addressable](/source/Byte_addressing) in [IBM System/360](/source/IBM_System/360) mainframes and their successors, including z/Architecture mainframes. This kind of memory is termed "Central Storage". IBM mainframe processors through much of the 1980s and 1990s supported another kind of memory: Expanded Storage. It was first introduced with the [IBM 3090](/source/IBM_3090) high-end mainframe series in 1985.[30]

Expanded Storage is 4KB-page addressable. When an application wants to access data in Expanded Storage it must first be moved into Central Storage. Similarly, data movement from Central Storage to Expanded Storage is done in multiples of 4 KB pages. Initially page movement was performed using relatively expensive instructions, by paging subsystem code.

The overhead of moving single and groups of pages between Central and Expanded Storage was reduced with the introduction of the [MVPG](#MVPG) (Move Page) instruction and the [ADMF](#ADMF) (Asynchronous Data Mover Facility) capability.

The MVPG instruction and ADMF are explicitly invoked—generally by middleware in [z/OS](/source/Z/OS) or [z/VM](/source/Z/VM) (and ACP?)—to access data in expanded storage. Some uses are namely:

- MVPG is used by [VSAM](/source/VSAM) Local Shared Resources (LSR) buffer pool management to access buffers in a hiperspace in Expanded Storage.
- Both MVPG and ADMF are used by [IBM Db2](/source/IBM_Db2) to access hiperpools. Hiperpools are portions of a buffer pool located in a hiperspace.
- VM Minidisk Caching.

Until the mid-1990s Central and Expanded Storage were physically different areas of memory on the processor. Since the mid-1990s Central and Expanded Storage were merely assignment choices for the underlying processor memory. These choices were made based on specific expected uses: For example, Expanded Storage is required for the Hiperbatch function (which uses the MVPG instruction to access its hiperspaces).

In addition to the hiperspace and paging cases mentioned above there are other uses of expanded storage, including:

- Virtual I/O (VIO) to Expanded Storage which stored temporary data sets in simulated devices in Expanded Storage. (This function has been replaced by VIO in Central Storage.)
- VM Minidisk Caching.

[z/OS](/source/Z/OS) removed the support for Expanded Storage. All memory in z/OS is now Central Storage. [z/VM](/source/Z/VM) 6.4 fulfills Statement of Direction to drop support for all use of Expanded Storage.

### MVPG and ADMF

#### MVPG

IBM described **MVPG** as "moves a single page and the central processor cannot execute any other instructions until the page move is completed."[31]

The MVPG mainframe instruction[32] (**M**o**V**e **P**a**G**e, opcode X'B254') has been compared to the **MVCL** (**M**o**V**e **C**haracter **L**ong) instruction, both of which can move more than 256 bytes within main memory using a single instruction. These instructions do not comply with definitions for [atomicity](/source/Atomicity_(programming)), although they can be used as a single instruction within documented timing and non-overlap restrictions.[33]: Note 8, page 7–27[34]

The need to move more than 256 bytes within main memory had historically been addressed with software[35] (MVC loops), MVCL,[36] which was introduced with the 1970 announcement of the [System/370](/source/IBM_System/370), and MVPG, patented[37] and announced by IBM in 1989, each have advantages.[38]

#### ADMF

**ADMF** (Asynchronous Data Mover Facility), which was introduced in 1992, goes beyond the capabilities of the MVPG (Move Page) instruction, which is limited to a single page,[39] and can move groups of pages between Central and Expanded Storage.

A [macro instruction](/source/Macro_instruction) named IOSADMF, which has been described as an [API](/source/Application_programming_interface) that avoids "direct, low-level use of ADMF",[40] can be used to read[h] or write data to or from a hiperspace.[41] Hiperspaces are created using DSPSERV CREATE.

To provide [reentrancy](/source/Reentrancy_(computing)), IOSADMF is used together with a "List form" and "Execute form."[42]

## Non-IBM implementations

Platform Solutions Inc. (PSI) previously marketed [Itanium](/source/Itanium)-based servers which were compatible with z/Architecture. IBM bought PSI in July 2008, and the PSI systems are no longer available.[43] [FLEX-ES](/source/FLEX-ES), [zPDT](/source/ZPDT) and the [Hercules emulator](/source/Hercules_emulator) also implement z/Architecture. [Hitachi](/source/Hitachi) mainframes running newer releases of the [VOS3](/source/Hitachi_VOS3) operating system implement ESA/390 plus Hitachi-unique CPU instructions, including a few 64-bit instructions. While Hitachi formally collaborated with IBM on the z900-G2/z800 CPUs introduced in 2002, Hitachi's machines are not z/Architecture-compatible.

## Notes

1. The ESA asynchronous-pageout, asynchronous-data-mover, program-call-fast, and [ESA/390](/source/ESA/390) vector facilities are not present in z/Architecture. The z/Architecture vector feature has been replaced by a very different vector facility starting with the [z13](/source/IBM_z13).

1. For a complete list see Chapter 1. Introduction in Principle of Operation.[3][44]

1. Although the PSW in z is a quadword and in older architectures a double word, IBM has always used the nomenclature *Program-Status Word* for this register.

1. Despite the similarity in name, Vector Facility for z/Architecture is not compatible with the [Vector Facility](/source/IBM_3090#Vector_facility) on the [3090](/source/IBM_3090).

1. Except for general register 0.

1. Some instructions allow references to unaligned data.

1. References to the first page in ESA mode, but that is not available on current models.

1. AREAD – transfer data from a hiperspace to the program's primary address space.

## References

**z-0**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr000.pdf). First ed. [IBM](/source/IBM). December 2000. SA22-7832-00. Retrieved August 11, 2025.
**z-1**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr001.pdf). Second ed. [IBM](/source/IBM). October 2001. SA22-7832-01. Retrieved August 11, 2025.
**z-2**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr002.pdf). Third ed. [IBM](/source/IBM). June 2003. SA22-7832-02. Retrieved August 11, 2025.
**z-3**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr003.pdf). Fourth ed. [IBM](/source/IBM). May 2004. SA22-7832-03. Retrieved August 11, 2025.
**z-6**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr006.pdf). Seventh ed. [IBM](/source/IBM). February 2008. SA22-7832-06. Retrieved August 11, 2025.
**z-7**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr007.pdf). Eighth ed. [IBM](/source/IBM). February 2009. SA22-7832-07. Retrieved August 11, 2025.
**z-8**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr008.pdf). Ninth ed. [IBM](/source/IBM). August 2010. SA22-7832-08. Retrieved August 11, 2025.
**z-9**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr009.pdf). Tenth ed. [IBM](/source/IBM). September 2012. SA22-7832-09. Retrieved August 11, 2025.
**z-10**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf). Eleventh ed. [IBM](/source/IBM). March 2015. SA22-7832-10. Retrieved August 11, 2025.
**z-11**- [*z/Architecture Principles of Operation*](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr011.pdf). Twelfth ed. [IBM](/source/IBM). September 2017. SA22-7832-11. Retrieved August 11, 2025.
**z-12**- [*z/Architecture Principles of Operation*](https://www.vm.ibm.com/library/other/22783212.pdf). Thirteenth ed. [IBM](/source/IBM). September 2019. SA22-7832-12. Retrieved August 11, 2025.
**z-13**- [*z/Architecture Principles of Operation*](https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-13.pdf). Fourteenth ed. [IBM](/source/IBM). May 2022. SA22-7832-13. Retrieved August 11, 2025.
**z-14**- [*z/Architecture Principles of Operation*](https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf). Fifteenth ed. [IBM](/source/IBM). April 2025. SA22-7832-14. Retrieved July 3, 2025.
**z**- [*z/Architecture Principles of Operation*](https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf). Fifteenth ed. [IBM](/source/IBM). April 2025. SA22-7832-14. Retrieved July 3, 2025.

1. ["Development and Attributes of z/Architecture"](https://www.cl.cam.ac.uk/teaching/0607/CompArch/ibm-z-plambeck.pdf). *IBM Journal of Research and Development*. **45** (4/5). July–September 2002. [Archived](https://web.archive.org/web/20131212140538/https://www.cl.cam.ac.uk/teaching/0607/CompArch/ibm-z-plambeck.pdf) 2013-12-12 at the Wayback Machine.

1. ["Accommodate functions for the z13 server to be discontinued on future servers"](https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.e0zm100/z132012hw1.htm). *[IBM](/source/IBM)*. 25 June 2015. [Archived](https://web.archive.org/web/20170915023438/https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.e0zm100/z132012hw1.htm) 2017-09-15 at the Wayback Machine. Retrieved 2017-09-18.

1. z-14, pp. 1–2 – 1–7.

1. z-4, pp. 1–7 – 1–31.

1. z-10, [xxviii](https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf#page=30).

1. ["IBM z Systems Processor Optimization Primer"](https://www.ibm.com/developerworks/community/files/form/anonymous/api/library/ff4563be-756e-49bf-9de9-6a04a08026f1/document/3dff8d34-fcf9-4939-9efc-11f15a3ce0f8/media/IBM%2520z%2520Systems%2520Processor%2520Optimization%2520Primer.pdf). *[IBM](/source/IBM)*

1. z-0, 16.

1. z-14, pp. 1–23.

1. z-14, pp. 26–1 – 26–126.

1. z, pp. 5–50.

1. z, pp. [4–46](https://www.vm.ibm.com/library/other/22783213.pdf#page=246).

1. z, pp. 4–9 – 4–11.

1. z, pp. 3–22–3–23.

1. z, pp. 4–5 – 4–8.

1. z, pp. 4–8.

1. z, pp. 6–15 – 6–16.

1. z, pp. 4–46 [4–46](https://www.vm.ibm.com/library/other/22783213.pdf#page=246).

1. z, pp. [4–9–4–12](https://www.vm.ibm.com/library/other/22783213.pdf#page=209).

1. z, pp. 2–5 – 2–6.

1. z, pp. [3–41, 3–42](https://www.vm.ibm.com/library/other/22783213.pdf#page=147).

1. [Preview: IBM z/VM V6.1 – Foundation for future virtualization growth](https://www.ibm.com/common/ssi/rep_ca/7/897/ENUS209-207/ENUS209-207.PDF) [Archived](https://web.archive.org/web/20211028213436/https://www.ibm.com/common/ssi/rep_ca/7/897/ENUS209-207/ENUS209-207.PDF) 2021-10-28 at the Wayback Machine, IBM United States Software Announcement 209-207, dated July 7, 2009

1. ALS 1 was 9672 G2; ALS 2 was 9672 G5; ALS 3 was the original z/Architecture:["IBM CMOS Processor Table"](https://www.vm.ibm.com/devpages/jelliott/cmosproc.html). November 18, 2008. [Archived](https://web.archive.org/web/20131210190707/http://www.vm.ibm.com/devpages/jelliott/cmosproc.html) 10 December 2013 at the Wayback Machine. Retrieved 18 October 2012.

1. ["IBM System z10 Business Class (z10 BC) Reference Guide"](https://www.ibm.com/systems/in/resources/systems_ap_z_hardware_z10bc_index_content_zs003021usen.pdf). *[IBM](/source/IBM)*. 2008. [Archived](https://web.archive.org/web/20110304060145/http://www-03.ibm.com/systems/in/resources/systems_ap_z_hardware_z10bc_index_content_zs003021usen.pdf) 2011-03-04 at the Wayback Machine. Retrieved 2012-10-18.

1. ["z/Architecture Principles of Operation"](https://publibfp.boulder.ibm.com/epubs/pdf/dz9zr010.pdf). [Archived](https://web.archive.org/web/20201130225514/http://publibfp.boulder.ibm.com/epubs/pdf/dz9zr010.pdf) 2020-11-30 at the Wayback Machine. Retrieved 2016-01-15.

1. Hoskins, Jim & Frank, Bob (2002). [*Exploring IBM Eserver Zseries and S/390 Servers*](https://books.google.com/books?id=NtHhpIjIFMEC&pg=PA26). Maximum Press. p. 26. ISBN 1885068913. [Archived](https://web.archive.org/web/20210427054109/https://books.google.com/books?id=NtHhpIjIFMEC&pg=PA26) 2021-04-27 at the Wayback Machine. Retrieved 2017-10-19. VM Data Spaces architecture is standard on all System/390 processors.

1. "CA Defends VSE Policy". *InformationWeek*. October 21, 1991. p. 15. Computer Associates International is now providing data space technology to VSE/ESA or System/370 users.

1. ["Analyzing data in memory"](https://www.ibm.com/docs/en/zp-and-ca/3.1.0?topic=resources-analyzing-data-in-memory). IBM.

1. Hemanth Nandas (October 15, 2007). ["What is hiperspace? Which was the first OS to support hiperspace?"](https://ibmmainframes.com/about25176.html#ixzz4WnbYLLq4). ibmmainframes.com. [Archived](https://web.archive.org/web/20170202024636/http://ibmmainframes.com/about25176.html#ixzz4WnbYLLq4) February 2, 2017 at the Wayback Machine. Retrieved January 25, 2017. HIGH PERFORMANCE SPACE or "High Performance Dataspace" (author Anuj Dhawan, same date)

1. ["CheatSheet #54 zTidBits z/OS Extended Addressing"](https://web.archive.org/web/20230506232032/http://zseries.marist.edu/pdfs/ztidbitz/54%20zTidBits%20(zOS%20ExtendedAddressability).pdf). Archived from [the original](http://zseries.marist.edu/pdfs/ztidbitz/54%20zTidBits%20%28zOS%20ExtendedAddressability%29.pdf) on 2023-05-06. Retrieved 2022-07-17.

1. Sakaki, M.; Samukawa, H.; Honjou, N. (1988). ["Effective utilization of IBM 3090 large virtual storage in the numerically intensive computations of ab initio molecular orbitals"](https://ieeexplore.ieee.org/document/5387596). *IBM Systems Journal*. **27** (4): 528–540. [doi:10.1147/sj.274.0528](https://doi.org/10.1147/sj.274.0528). [ISSN 0018-8670](https://www.worldcat.org/issn/0018-8670)

1. ["HLASM – MVPG = MoVe PaGe"](https://www.bixoft.nl/english/opcd/mvpg.htm). [Archived](https://web.archive.org/web/20131006113734/http://www.bixoft.nl/english/opcd/mvpg.htm) 2013-10-06 at the Wayback Machine. Retrieved 2017-01-24.

1. MOVE LONG, note 8.["GA22-7000-10, IBM System/370, Principles of Operation"](http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf). [Archived](https://web.archive.org/web/20210411000251/http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf) 2021-04-11 at the Wayback Machine. Retrieved 2021-10-11.

1. "things are done immediately, and there is no chance of the instruction being half-completed or of another being interspersed. Used especially to convey that an operation cannot be interrupted."["Atomic from FOLDOC"](https://www.foldoc.org/atomic)

1. ["$MVCL – Move more than 256 bytes of storage"](https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.hasc200/hasc2__MVCL_____Move_more_than_256_bytes_of_storage.htm). *[IBM](/source/IBM)*. 20 September 2014. [Archived](https://web.archive.org/web/20170202033701/https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.hasc200/hasc2__MVCL_____Move_more_than_256_bytes_of_storage.htm) 2 February 2017 at the Wayback Machine. Retrieved 24 January 2017.

1. ["Move Long"](http://csc.columbusstate.edu/woolbright/Instructions/MVCL.HTM). [Archived](https://web.archive.org/web/20170427234006/http://csc.columbusstate.edu/woolbright/Instructions/MVCL.HTM) 2017-04-27 at the Wayback Machine. Retrieved 2017-01-24.

1. ["MVPG faster than MVCL for aligned pages?"](https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/Y-P4xYn3n-0). [Archived](http://arquivo.pt/wayback/20110122130054/https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/Y-P4xYn3n-0) 2011-01-22 at the Wayback Machine. Retrieved 2017-01-24.

1. IBM's patent EP0549924A1 describes MVPG as "moves a single page."

1. Celestini, Art (August 20, 1997). ["admf"](https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/oavv1AfA6oA). [Archived](http://arquivo.pt/wayback/20110122130054/https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/oavv1AfA6oA) 2011-01-22 at the Wayback Machine. Retrieved 2017-01-24. – via Google Groups.

1. z/OS MVS Programming: Extended Addressability Guide – SA23-1394-00

1. ["IOSADMF — Transfer hiperspace data"](https://www.ibm.com/support/knowledgecenter/SSLTBW_2.1.0/com.ibm.zos.v2r1.ieaa200/iosadmf.htm). *[IBM](/source/IBM)*. February 7, 2015. [Archived](https://web.archive.org/web/20170202032953/http://www.ibm.com/support/knowledgecenter/SSLTBW_2.1.0/com.ibm.zos.v2r1.ieaa200/iosadmf.htm) 2 February 2017 at the Wayback Machine. Retrieved January 24, 2017.

1. ["IBM Acquires Platform Solutions"](https://web.archive.org/web/20080905095542/http://www-03.ibm.com/press/us/en/pressrelease/24560.wss). IBM. 2008-07-02. Archived from [the original](https://www-03.ibm.com/press/us/en/pressrelease/24560.wss) on 2008-09-05. Retrieved 2008-09-06.

1. z-14, pp. 1–7 – 1–31.

## Further reading

- [Preshing on Programming – Atomic vs. Non-Atomic Operations](https://preshing.com/20130618/atomic-vs-non-atomic-operations)
- [Principles of Computer Design – Atomicity](https://ocw.mit.edu/courses/res-6-004-principles-of-computer-system-design-an-introduction-spring-2009/de2b7c59e413f58e51eac60acd52efef_atomicity_open_5_0.pdf)

---
Adapted from the Wikipedia article [Z/Architecture](https://en.wikipedia.org/wiki/Z%2FArchitecture) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Z%2FArchitecture?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.