# Write combining

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> Source: https://en.wikipedia.org/wiki/Write_combining
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{{Short description|Computing technique}}
{{refimprove|date=April 2012}}
'''Write combining''' ('''WC''')<ref>{{cite web|url=http://download.intel.com/design/PentiumII/applnots/24442201.pdf|title=Write Combining Memory Implementation Guidelines|publisher=Intel|author=Intel|date=November 1998|accessdate=2010-11-02}}</ref> is a [computer bus](/source/computer_bus) technique for allowing [data](/source/data) to be combined and temporarily stored in a [buffer](/source/buffer_(computer_science)){{snd}} the '''write combine buffer''' ('''WCB'''){{snd}} to be released together later in [burst mode](/source/burst_mode_(computing)) instead of writing (immediately) as single [bit](/source/bit)s or small chunks.

==Technique==
Write combining cannot be used for general memory access (data or code regions) due to the [weak ordering](/source/weak_ordering). Write-combining does not guarantee that the combination of writes and reads is done in the expected order. For example, a <code>write</code>/<code>read</code>/<code>write</code> combination to a specific address would lead to the write combining order of <code>read</code>/<code>write</code>/<code>write</code> which can lead to obtaining wrong values with the first read (which potentially relies on the write before).

In order to avoid the problem of read/write order described above, the [write buffer](/source/write_buffer) can be treated as a [fully associative](/source/fully_associative) [cache](/source/CPU_cache) and added into the [memory hierarchy](/source/memory_hierarchy) of the device in which it is implemented.<ref>{{cite web|url=http://www.bearwindows.boot-land.net/af.htm|archive-url=https://web.archive.org/web/20080724002604/http://www.bearwindows.boot-land.net/af.htm|url-status=usurped|archive-date=July 24, 2008|title=Video Hardware Acceleration in DOS Environment|publisher=BearWindows Vault|author=BearWindows|date=2008-09-01|accessdate=2010-11-02}}</ref>
Adding complexity slows down the [memory hierarchy](/source/memory_hierarchy) so this technique is often only used for memory which does not need [strong ordering](/source/strong_ordering) (always correct) like the [frame buffer](/source/frame_buffer)s of [video cards](/source/video_cards).

==See also==
*[Framebuffer](/source/Framebuffer) (FB), and when linear: LFB
*[Memory type range register](/source/Memory_type_range_register)s (MTRR) – the older x86 cache control mechanism
*[Page attribute table](/source/Page_attribute_table) (PAT) – x86 page table extension that allows fine-grained cache control, including write combining
*[Page table](/source/Page_table)
*[Uncacheable speculative write combining](/source/Uncacheable_speculative_write_combining) (USWC)
*[Video Graphics Array](/source/Video_Graphics_Array) (VGA), and Banked (BVGA) Frame Buffer

==References==
{{Reflist}}

==External links==
*[http://www.mdgx.com/umb.htm#FAS 6x86opt, ctppro, CTU, DirectNT, FastVid, fstorion, K6Speed, MTRRLFBE, S3 Speed Up & Write Allocate Monitor] enable [LFB](/source/Framebuffer) and BVGA Write Combining on Intel Pentium Pro/2/3/4 and AMD K6 [CPU](/source/Central_processing_unit)s in Windows 9x, Windows NTx, DOS, OS/2 and Linux
*[http://rayer.g6.cz/programm/programe.htm#MTRRLFBE MTRRLFBE] enable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 CPUs in Windows 9x and DOS
*[https://web.archive.org/web/20030820203630/http://home.student.utwente.nl/r.muller/unirefresh/ctu/ CTU] (Internet Archive cached copy) enable LFB and Banked VGA Write Combining on AMD K6 CPUs in Windows 9x and DOS

Category:Computer buses
Category:Computer memory

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Adapted from the Wikipedia article [Write combining](https://en.wikipedia.org/wiki/Write_combining) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Write_combining?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.