# Wafer testing

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**Wafer testing** is a step performed during [semiconductor device fabrication](/source/Fabrication_(semiconductor)) after [back end of line (BEOL)](/source/Back_end_of_line) and before [IC packaging](/source/IC_packaging).

Two types of testing are typically done. Very basic wafer parametric tests (WPT) are performed at a few locations on each wafer to ensure the wafer fabrication process has been carried out successfully. Discrete test structures are provided for WPT to test parameters like transistor [threshold voltage](/source/Threshold_voltage) or gain, interconnect resistance, capacitance, diodes, etc. Considerable information about device performance is obtained from WPT using structured typically provided in the scribe lines.[1][2][3]

After WPT, all individual [integrated circuits](/source/Integrated_circuits) on the wafer are given extensive wafer [functional testing](/source/Functional_testing) (WFT) (also called die sort) by applying special [test patterns](/source/Automatic_test_pattern_generation). The testers used for WFT are typically quite expensive (see [Teradyne](/source/Teradyne) for an example of a semiconductor test system). The WFT "yield" is recognized as the key test in determining the economic outcome of the entire fabrication process.

## Wafer prober

Both WPT and WFT are performed using a wafer handler called a [wafer prober](/source/Wafer_prober). The wafer prober brings an array of microscopic needles or probes called a [probe card](/source/Probe_card) into [electrical contact](/source/Electrical_contact) with the wafer (vacuum-mounted on a wafer chuck). WPT and WFT use different probe cards, the WFT card contacts a chip's bond pads. After each test the prober moves the wafer to the next testing location. The wafer prober is responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the [contact pads](/source/Contact_pad) on the wafer and the tips of the probes.

## Testing

When all test patterns pass for a specific die, its position is remembered for later use during [IC packaging](/source/Integrated_circuit_packaging). Historically, non-passing circuits were marked with a small dot of ink in the middle of the die, today this information is stored in a file, named a wafermap. This wafermap is then sent to the [die attachment](/source/Die_attachment) process which then only selects good dies. When ink dots were used, vision systems on subsequent die handling equipment recognized the ink dot. For today's multi-die packages such as stacked [chip-scale package](/source/Chip-scale_package) (SCSP) or system in package (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.

In some specific cases, a chip that passes some but not all tests can still be used as a product with limited functionality. The most common example of this is a memory chip for which only one part of the memory is functional. In this case, the chip can sometimes still be sold as a lower cost part with a smaller amount of memory. In other specific cases, a defective chip may be repaired (e.g. by laser repair) using redundant spare circuitry.

After IC packaging, a packaged chip will be tested again during the [IC testing](/source/Semiconductor_fabrication#Device_test) phase, usually with the same or very similar tests and tester as for WFT. For this reason, it may be thought that WFT is an unnecessary, redundant step. This is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when WFT yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and chips undergo blind assembly.

## See also

- [Bond characterization](/source/Bond_characterization)
- [Non-contact wafer testing](/source/Non-contact_wafer_testing)

## References

1. ["Startup enables IC variability characterization"](http://www.eetasia.com/ART_8800419948_480100_NT_648c3def.HTM) by Richard Goering 2006

1. ["Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry"](http://www2.computer.org/portal/web/csdl/doi/10.1109/ATS.2008.68) (abstract)

1. *Design for Manufacturability And Statistical Design: A Constructive Approach*, by Michael Orshansky, Sani Nassif, Duane Boning 2007. ISBN 0-387-30928-4 ISBN 978-0-387-30928-6 [\[1\]](https://books.google.com/books?id=sZ-NPuM-ScYC&dq=scribe+line+test+structures&pg=PA84) p. 84

## Bibliography

- Fundamentals of Digital Semiconductor Testing (Version 4.0) by Guy A. Perry (Spiral-bound – Mar 1, 2003) ISBN 978-0965879705
- Principles of Semiconductor Network Testing (Test & Measurement) (Hardcover)by Amir Afshar, 1995 ISBN 978-0-7506-9472-8
- Power-Constrained Testing of VLSI Circuits. A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing) by Nicola Nicolici and Bashir M. Al-Hashimi (Kindle Edition – Feb 28, 2003) ISBN 978-0-306-48731-6
- Semiconductor Memories: Technology, Testing, and Reliability by Ashok K. Sharma (Hardcover – Sep 9, 2002) ISBN 978-0780310001

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Adapted from the Wikipedia article [Wafer testing](https://en.wikipedia.org/wiki/Wafer_testing) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Wafer_testing?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.