# Vision processing unit > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Vision_processing_unit > Markdown URL: https://mediated.wiki/source/Vision_processing_unit.md > Source: https://en.wikipedia.org/wiki/Vision_processing_unit > Source revision: 1344423443 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) {{short description|Emerging class of microprocessor}} A '''vision processing unit''' ('''VPU''') is (as of 2023) an emerging class of [microprocessor](/source/microprocessor); it is a specific type of [AI accelerator](/source/AI_accelerator), designed to [accelerate](/source/hardware_acceleration) [machine vision](/source/machine_vision) tasks.{{cite web|title= A third type of processor for AR/VR: Movidius' Myriad 2 VPU|url=http://www.tomshardware.com/news/movidiud-myriad2-vpu-vision-processing-vr,30850.html|author=Seth Colaner|author2=Matthew Humrick|date=January 3, 2016|work=Tom's Hardware}}{{cite web|title=The rise of VPUs: Giving Eyes to Machines|url=http://www.digit.in/general/the-rise-of-vpus-giving-eyes-to-machines-29561.html|work=Digit.in|author=Prasid Banerje|date=March 28, 2016|access-date=April 18, 2016|archive-date=September 2, 2017|archive-url=https://web.archive.org/web/20170902012608/http://www.digit.in/general/the-rise-of-vpus-giving-eyes-to-machines-29561.html|url-status=dead}} == Overview == Vision processing units are distinct from [graphics processing unit](/source/graphics_processing_unit)s (which are specialised for [video encoding and decoding](/source/Video_codec)) in their suitability for running [machine vision algorithms](/source/machine_vision) such as CNN ([convolutional neural network](/source/convolutional_neural_network)s) and SIFT ([scale-invariant feature transform](/source/scale-invariant_feature_transform)). They may include [direct interfaces](/source/interface_(computing)) to take data from [cameras](/source/digital_cameras) (bypassing any off chip buffers), and have a greater emphasis on on-chip [dataflow](/source/dataflow) between many [parallel execution units](/source/parallel_execution_units) with [scratchpad memory](/source/scratchpad_memory), like a [spatial architecture](/source/spatial_architecture) or a [manycore](/source/Manycore_processor) [DSP](/source/digital_signal_processor). But, like video processing units, they may have a focus on [low precision](/source/low_precision) [fixed point arithmetic](/source/fixed_point_arithmetic) for [image processing](/source/image_processing). == Contrast with GPUs == They are distinct from [GPU](/source/GPU)s, which contain specialised hardware for [rasterization](/source/rasterization) and [texture mapping](/source/texture_mapping) (for [3D graphics](/source/3D_graphics)), and whose [memory architecture](/source/memory_architecture) is optimised for manipulating [bitmap images](/source/bitmap_images) in [off-chip memory](/source/off-chip_memory) (reading [textures](/source/texture_map), and modifying [frame buffers](/source/frame_buffers), with [random access patterns](/source/locality_of_reference)). VPUs are optimized for performance per watt, while GPUs mainly focus on absolute performance. Target markets are [robotics](/source/robotics), the [internet of things](/source/internet_of_things) (IoT), new classes of [digital cameras](/source/digital_cameras) for [virtual reality](/source/virtual_reality) and [augmented reality](/source/augmented_reality), [smart camera](/source/smart_camera)s, and integrating machine vision acceleration into [smartphone](/source/smartphone)s and other [mobile devices](/source/mobile_devices). == Examples == * [Movidius Myriad X](/source/Movidius_Myriad_X), which is the third-generation vision processing unit in the Myriad VPU line from [Intel Corporation](/source/Intel).{{Cite web|url=https://www.intel.com/content/www/us/en/products/details/processors/movidius-vpu.html|title=Intel® Movidius™ Vision Processing Units (VPUs)|website=Intel}} * [Movidius Myriad 2](/source/Movidius_Myriad_2), which finds use in [Google Project Tango](/source/Google_Project_Tango),{{cite web|last1=Weckler|first1=Adrian|title=Dublin tech firm Movidius to power Google's new virtual reality headset|url=http://www.independent.ie/business/technology/news/dublin-tech-firm-movidius-to-power-googles-new-virtual-reality-headset-34449883.html|website=Independent.ie|date=14 February 2016 |access-date=15 March 2016}} [Google Clips](/source/Google_Clips) and DJI drones{{cite web|url=https://www.movidius.com/news/dji-brings-two-new-flagship-drones-to-lineup-featuring-myriad-2-vpus|title=DJI Brings Two New Flagship Drones to Lineup Featuring Myriad 2 VPUs - Machine Vision Technology - Movidius|website=www.movidius.com}} *[Pixel Visual Core](/source/Pixel_Visual_Core) (PVC), which is a fully programmable [Image](/source/Image_processor), Vision and [AI](/source/AI_accelerator) processor for mobile devices * [Microsoft HoloLens](/source/Microsoft_HoloLens), which includes an accelerator referred to as a ''holographic processing unit'' (complementary to its CPU and GPU), aimed at interpreting camera inputs, to accelerate environment tracking and vision for augmented reality applications.{{cite web|url=http://www.pcworld.com/article/2917512/microsoft-designed-a-special-processor-to-handle-hololens-data.html|title=Microsoft dives deeper into HoloLens details: 'Holographic processor' role revealed|date=May 1, 2015|author=Fred O'Connor|work=PCWorld}} * [Eyeriss](/source/Eyeriss), a [spatial architecture](/source/spatial_architecture) designed from [MIT](/source/MIT) intended for running [convolutional neural network](/source/convolutional_neural_network)s.{{cite web|url=https://www.mit.edu/~sze/eyeriss.html|title=Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks|author=Chen, Yu-Hsin|author2=Krishna, Tushar|author3=Emer, Joel|author4=Sze, Vivienne|author4-link=Vivienne Sze|name-list-style=amp|work=IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers|year=2016|pages=262–263}} * [NeuFlow](/source/NeuFlow), a design by [Yann LeCun](/source/Yann_LeCun) (implemented in [FPGA](/source/FPGA)) for accelerating [convolutions](/source/convolutions), using a dataflow architecture. * [Mobileye EyeQ](/source/Mobileye_EyeQ), by [Mobileye](/source/Mobileye) * Programmable Vision Accelerator (PVA), a [7-way VLIW Vision Processor](/source/7-way_VLIW_Vision_Processor) designed by [Nvidia](/source/Nvidia). == Broader category == {{main|AI accelerator}} Some processors are not described as VPUs, but are equally applicable to machine vision tasks. These may form a broader category of [AI accelerators](/source/AI_accelerator_(computer_hardware)) (to which VPUs may also belong), however as of 2016 there is no consensus on the name: * [IBM](/source/IBM) [TrueNorth](/source/TrueNorth), a [neuromorphic](/source/neuromorphic) processor aimed at similar sensor data [pattern recognition](/source/pattern_recognition) and intelligence tasks, including video/audio. * [Qualcomm Zeroth Neural processing unit](/source/Qualcomm_Zeroth_Neural_processing_unit), another entry in the emerging class of sensor/AI oriented chips.{{cite web|title=Introducing Qualcomm Zeroth Processors: Brain-Inspired Computing|url=https://www.qualcomm.com/news/onq/2013/10/10/introducing-qualcomm-zeroth-processors-brain-inspired-computing|date=October 10, 2013|work=Qualcomm}} * All models of Intel [Meteor Lake](/source/Meteor_Lake) processors have a [Versatile Processor Unit](/source/Versatile_Processor_Unit) (VPU) built-in for accelerating [inference](/source/statistical_inference) for computer vision and deep learning.{{Cite web|url=https://www.pcmag.com/news/intel-to-bring-a-vpu-processor-unit-to-14th-gen-meteor-lake-chips|title=Intel to Bring a 'VPU' Processor Unit to 14th Gen Meteor Lake Chips|website=PCMAG|date=August 2022 }} == See also == * [Adapteva Epiphany](/source/Adapteva_Epiphany), a manycore processor with similar emphasis on on-chip dataflow, focussed on 32-bit floating point performance * [CELL](/source/CELL), a multicore processor with features fairly consistent with vision processing units (SIMD instructions & datatypes suitable for video, and on-chip DMA between scratchpad memories) * [Coprocessor](/source/Coprocessor) * [Graphics processing unit](/source/Graphics_processing_unit), also commonly used to run vision algorithms. NVidia's Pascal architecture includes FP16 support, to provide a better precision/cost tradeoff for AI workloads * [MPSoC](/source/MPSoC) * [OpenCL](/source/OpenCL) * [OpenVX](/source/OpenVX) * [Physics processing unit](/source/Physics_processing_unit), a past attempt to complement the CPU and GPU with a high throughput accelerator * [Tensor Processing Unit](/source/Tensor_Processing_Unit), a chip used internally by Google for accelerating AI calculations ==References== {{reflist}} ==External links== * [http://eyeriss.mit.edu Eyeriss architecture] * [http://whatis.techtarget.com/definition/holographic-processing-unit-HPU Holographic processing unit] * [http://pub.clement.farabet.net/ecvw11.pdf NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision] {{Webarchive|url=https://web.archive.org/web/20170505184615/http://pub.clement.farabet.net/ecvw11.pdf |date=2017-05-05 }} {{Differentiable computing}} Category:Microprocessors Category:Neural processing units Category:Machine vision --- Adapted from the Wikipedia article [Vision processing unit](https://en.wikipedia.org/wiki/Vision_processing_unit) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Vision_processing_unit?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.