# Video display controller

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{{Short description|Type of integrated circuit}}
{{More citations needed|date=December 2015}}
[[File:NECuPD7220BlockDiagram.svg|thumb|right|upright=1.7|Block diagram of the [NEC μPD7220](/source/NEC_%CE%BCPD7220) (released in 1981) graphics display controller]]

A '''video display controller''' ('''VDC'''), also called a '''display engine''' or '''display interface''', is an [integrated circuit](/source/integrated_circuit) which is the main component in a [video-signal generator](/source/video-signal_generator), a device responsible for the production of a [TV](/source/Television) [video signal](/source/Composite_video) in a computing or game system. Some VDCs also generate an [audio signal](/source/audio_signal), but that is not their main function. VDCs were used in the [home computer](/source/home_computer)s of the 1980s and also in [game console](/source/game_console)s and [arcade game](/source/arcade_game)s.

The VDC is the main component of the video signal generator logic, responsible for generating the timing of video signals such as the horizontal and vertical [synchronization signal](/source/Component_video_sync)s and the [blanking interval](/source/Video_formats) signal. Sometimes other supporting chips were necessary to build a complete system, such as [RAM](/source/Random-access_memory) to hold [pixel](/source/pixel) [data](/source/bitmap), [ROM](/source/Read-only_memory) to hold [character fonts](/source/computer_font), or some [discrete logic](/source/Transistor%E2%80%93transistor_logic) such as [shift register](/source/shift_register)s.

Most often the VDC chip is used as an extension to a host computer system, and is completely integrated to the host, with the memory holding the graphics data appearing in the same [memory map](/source/memory_map) of the main CPU. This allows the CPU to write new data to memory which the VDC then reads and displays. In some cases, the VDC functions as a [coprocessor](/source/coprocessor) that can manipulate the RAM contents independently. Due to the low performance of early [dynamic RAM](/source/dynamic_RAM), some VDCs used an entirely separate DRAM pool that it could read without interrupting or being interrupted by the CPU. Later systems used [dual-ported video RAM](/source/dual-ported_video_RAM) to avoid the performance issues, allowing the CPU to read or write memory from one port, while at the same time the VDC reads it from the other port.

==VDC vs. GPU==
The difference between a display controller, a graphics accelerator, blitter, and a [graphics processing unit](/source/graphics_processing_unit) (GPU) is often blurred by examples that are called one but have some features of another class.  It is not always clear when a particular video chip is a video display controller and when it is a video display processor. For example, the TMS9918 may be referred to either way, depending on the source.

Generally, a canonical VDC would not include any internal capability to perform graphics operations on its own, the ability to draw lines or fill areas for instance, and relies on the host CPU to perform these sorts of operations by performing those calculations and depositing the results in memory for the VDC to read. Blitters add some of these features, which requires additional registers and some math hardware on the IC to run these routines. Some chips ''called'' VDCs in the 1980 do include some of these features, which makes them technically closer to blitters, and the choice of terminology was largely due to the manufacturer preferring one term over the other.

VDCs and blitters were popular during the 1980s and into the 1990s. These VDCs often had special hardware for the creation of [sprites](/source/Sprite_(computer_graphics)). Early examples include the Atari's [ANTIC](/source/ANTIC) and the Texas Instruments [TMS9918](/source/TMS9918). Later designs generalized sprites by implementing [Bit Blitter](/source/Blitter) functions, including the [VDP2 32-bit background and scroll plane video display processor](/source/VDP2_32-bit_background_and_scroll_plane_video_display_processor) of the [Sega Saturn](/source/Sega_Saturn) and the [Lisa](/source/Amiga_Advanced_Graphics_Architecture) (AGA) chip that was used for the improved graphics of the later generation [Amiga](/source/Amiga) computers.

[Graphics processing unit](/source/Graphics_processing_unit)s (GPUs) take this evolution a step further, including not only more powerful math hardware, typically multiple [floating point unit](/source/floating_point_unit)s, but also include the ability to send custom routines to the GPU to be run locally. This means that a GPU not only has built-in routines for "draw line" or "rotate camera", but can also be sent entire programs like "draw airplane", which can then be performed with a single line of code. This allows the host program to dramatically lower the amount of information that has to be sent back and forth between the GPU and the host and can offer large performance improvements.

GPUs became popular during the 1990s, including the [S3 ViRGE](/source/S3_ViRGE), the [Matrox Mystique](/source/Matrox_Mystique), and the [Voodoo Graphics](/source/3dfx); though earlier examples such as the [NEC μPD7220](/source/NEC_%CE%BCPD7220) had already existed for some time. Modern systems all use a GPU-like display systems, sometimes built into the CPU, sometimes a separate IC on a larger motherboard, and sometimes on a separate card.

==Types==
Video display controllers can be divided in several different types, listed here from simplest to most complex;

*'''Video shifters''', or "video shift register based systems" (there is no generally agreed upon name for these types of devices), are the most simple type of video controllers.  They are directly or indirectly responsible for the video timing signals, but they normally do not access the video RAM directly. They get the video data from the main CPU, a byte at a time, and convert it to a serial bitstream, hence the technical name "video shifter". This serial data stream is then used together with the synchronization signals to output a video signal. The main CPU needs to do the bulk of the work. Normally these chips only support a very low resolution [raster graphics](/source/raster_graphics) mode.
* A '''CRTC''', or [cathode-ray tube](/source/cathode-ray_tube) controller, generates the video timings and reads video data from RAM attached to the CRTC to output it via an external character generator ROM (for [text mode](/source/text_mode)s) or directly to the video output shift register (for high resolution graphics modes).<ref name="Rasch_Slaughter_PC_Underground">{{cite book|author=M. Rasch, B. Bertelsons|editor=Scott Slaughter|title=PC Underground: Unconventional Programming Topics|year=1995|publisher=Abacus Software Inc|location=US|page=58-68|isbn=978-1557552754}} "Cathode Ray Tube Controller (CRTC) is responsible for generating the video signal and is programmable. CRTC-Registers bit meaning tables for [VGA](/source/Video_Graphics_Array), [EGA](/source/Enhanced_Graphics_Adapter), [CGA](/source/Color_Graphics_Adapter), [Hercules](/source/Hercules_Graphics_Card), [SVGA](/source/Super_VGA), [Mode X](/source/Mode_X)."</ref> Because the actual capabilities of the video generator depend to a large degree on the external logic, video generator based on a CRTC chip can have a wide range of capabilities, from simple text-mode only systems to high-resolution systems supporting a wide range of colours. Sprites, however, are normally not supported by these systems.
*'''Video interface controllers''' are much more complex than CRT controllers, and the external circuitry that is needed with a CRTC is embedded in the video controller chip. Sprites are often supported, as are (RAM based) [character generators](/source/Character_encoding) and video RAM dedicated to [colour attributes](/source/Character_encoding) and [palette registers](/source/Palette_(computing)) ([colour lookup tables](/source/CLUT)) for the high-resolution or text modes.
*'''Video coprocessors''' have their own internal CPU dedicated to reading (and writing) their own video RAM (which may be shared with the CPU), and converting the contents of this video RAM to a video signal. The main CPU can give commands to the coprocessor, for example to change the video modes or to manipulate the video RAM contents. The video coprocessor also controls the (most often RAM-based) character generator, the colour attribute RAM, palette registers, and the sprite logic (as long as these exist of course).

==List of example VDCs==
{{See also|List of home computers by video hardware|Sprite (computer graphics)}}

Examples of video display controllers are:

'''Video shifters'''
* The [RCA CDP1861](/source/RCA_CDP1861) was a very simple chip, built in [CMOS](/source/CMOS) technology (which was unusual for the mid-1970s) to complement the [RCA 1802](/source/RCA_1802) microprocessor, it was mainly used in the [COSMAC VIP](/source/COSMAC_VIP). It could only support a very low resolution monochrome graphic mode.
* The [Television Interface Adaptor](/source/Television_Interface_Adaptor) (TIA) is the custom video chip that is the heart of the [Atari 2600](/source/Atari_2600) game console, a primitive chip that relied on the 6502 microprocessor to do most of the work, also was used to generate the audio.

'''CRT Controllers'''
* The [Intel 8275](/source/Intel_8275) CRT controller was used in the [Convergent Technologies](/source/Convergent_Technologies) AWS / [Burroughs B20](/source/Burroughs_B20), along with some [S-100 bus](/source/S-100_bus) systems.
* The [Motorola 6845](/source/Motorola_6845) (MC6845) is a video address generator first introduced by [Motorola](/source/Motorola) and used for the [Amstrad CPC](/source/Amstrad_CPC), and the [BBC Micro](/source/BBC_Micro). It was also used for almost all the early video adapters for the PC, such as the [MDA](/source/IBM_Monochrome_Display_Adapter), [CGA](/source/Color_Graphics_Adapter) and [EGA](/source/Enhanced_Graphics_Adapter) adapters.  The MDA and CGA use an actual Motorola chip, while the EGA has a custom IBM chipset of five LSI chips; one of those chips includes IBM's reimplementation of the CRTC, which operates like an MC6845 but differs in a few register addresses and functions so it is not 100% compatible.  In all later [VGA](/source/Video_Graphics_Array) compatible adapters the function of the 6845 is still reproduced inside the video chip, so in a sense all current [IBM PC compatible](/source/IBM_PC_compatible) PCs still incorporate the logic of the 6845 CRTC.

'''Video interface controllers'''
* The [Signetics 2636](/source/Signetics_2636) and [2637](/source/Signetics_2637) are video controllers best known for their use in the [Interton VC 4000](/source/VC_4000) and [Emerson Arcadia 2001](/source/Arcadia_2001) respectively.
* The [MC6847](/source/MC6847) is a video display generator (VDG) first introduced by Motorola and used in the [TRS-80 Color Computer](/source/TRS-80_Color_Computer), [Dragon 32/64](/source/Dragon_32%2F64), [Laser 200](/source/Laser_200) and [Acorn Atom](/source/Acorn_Atom) among others.
* The [MOS Technology 6560 (NTSC) and 6561 (PAL)](/source/MOS_Technology_VIC) are known as the video interface controller (VIC) and used in the [VIC-20](/source/VIC-20).
* The [MOS Technology 6567/8562/8564 (NTSC versions) and 6569/8565/8566 (PAL)](/source/MOS_Technology_VIC-II) were known as the VIC-II and were used in the [Commodore 64](/source/Commodore_64).
* The [MOS Technology 8563](/source/MOS_Technology_8563)/[8568](/source/MOS_Technology_8568) was used in the [Commodore 128](/source/Commodore_128) (8563) and Commodore 128D (8568) to create an 80 column text display, as well as several high resolution graphics modes.  The Commodore 128 models included a [VIC-II](/source/VIC-II) to support [Commodore 64](/source/Commodore_64) compatible video modes.
* The [MOS Technology 7360](/source/MOS_Technology_TED) text editing device (TED) was used in the [Plus/4](/source/Plus%2F4), [Commodore 16](/source/Commodore_16) and [Commodore 116](/source/Commodore_116) computers and had an integrated audio capability.
* The [Philips semiconductors](/source/NXP_Semiconductors) SCC66470 was a VSC (Video- and Systems Controller) used in conjunction with their [68070](/source/Philips_68070)-Microcontroller e.g. in [CD-i](/source/CD-i) systems.

'''Video coprocessors'''
*The [ANTIC](/source/ANTIC) ('''''A'''lpha-'''N'''umeric '''T'''elevision '''I'''nterface '''C'''ircuit'') was an early video system chip used in [Atari 8-bit computers](/source/Atari_8-bit_computers). It could read a "[Display list](/source/Display_list)" with its own built in CPU and use this data to generate a complex video signal.
* The [TMS9918](/source/TMS9918) is known as the Video Display Processor (VDP) and was first designed for the [Texas Instruments](/source/Texas_Instruments) [TI-99/4](/source/TI-99%2F4), but was later also used in systems like the [MSX](/source/MSX) (MSX-1), [ColecoVision](/source/ColecoVision), [Memotech MTX series](/source/Memotech_MTX), and for the [Sega](/source/Sega) [SG-1000](/source/SG-1000) and [SC-3000](/source/SC-3000).  The [Master System](/source/Master_System) uses an enhanced VDP based on the TMS9918, and the Sega 315-5313 (Yamaha YM7101) VDP used in the [Sega Genesis](/source/Sega_Genesis) and some arcade machines is a further advancement of the Master System VDP with the original (inferior) TMS9918 modes removed.
* The [NEC μPD7220](/source/NEC_%CE%BCPD7220). Used in some high-end graphics boards for the IBM PC in the mid 80s, notably in products from [Number Nine Visual Technology](/source/Number_Nine_Visual_Technology).
* The RP2C02 ([NTSC](/source/NTSC))<ref>{{cite web |url=https://www.nesdev.org/wiki/NTSC_video |title=NES NTSC Video |publisher=NESdev.org |date=2024-06-04}}</ref> or RP2C07 ([PAL](/source/PAL))<ref>{{cite web |url=https://www.nesdev.org/wiki/PAL_video |title=NES PAL Video |publisher=NESdev.org |date=2024-06-24}}</ref> was a video coprocessor designed by [Ricoh](/source/Ricoh) for [Nintendo](/source/Nintendo)'s use in the Famicom and [Nintendo Entertainment System](/source/Nintendo_Entertainment_System). It was connected to 2048 [byte](/source/byte)s of dedicated video RAM, and had a dedicated address bus that allowed additional RAM or ROM to be accessed from the game cartridge. A scrollable playfield of 256×240 pixels was supported, along with a display list of 64 OBJs (sprites), of which 8 could be displayed per scanline.
* The [Yamaha V9938](/source/Yamaha_V9938) is an improved version of the TMS9918, and was mainly used in the [MSX2](/source/MSX).
* The [Yamaha V9958](/source/Yamaha_V9958) is the Video Display Processor (VDP) mainly used in the [MSX2+](/source/MSX) and [MSX turboR](/source/MSX) computers.
* The VLSI VS21S010D-L is a 128kB SPI/parallel SRAM with an integrated video display controller with variable-bit-depth pixels and a block-move blitter.
* The [Thomson EF936x](/source/Thomson_EF936x) series of Graphic Display Processor (GDP), which offers a draw rate of 1 million&nbsp;[pixel](/source/pixel)s&nbsp;per second and resolutions up to 1024×512.

==Alternatives to a VDC chip==
Note that many early home computers did not use a VDP chip, but built the whole video display controller from a lot of [discrete logic](/source/Transistor-transistor_logic) chips, (examples are the [Apple II](/source/Apple_II), [PET](/source/Commodore_PET), and [TRS-80](/source/TRS-80)). Because these methods are very flexible, video display generators could be very capable (or extremely primitive, depending on the quality of the design), but also needed a lot of components.

Many early systems used some form of an early [programmable logic array](/source/programmable_logic_array) to create a video system; examples include the [ZX Spectrum](/source/ZX_Spectrum) and [ZX81](/source/ZX81) systems and Elektronika [BK-0010](/source/BK-0010), but there were many others. Early implementations were often very primitive, but later implementations sometimes resulted in fairly advanced video systems, like the one in the [SAM Coupé](/source/SAM_Coup%C3%A9). On the lower end, as in the ZX81, the hardware would only perform electrical functions and the timing and level of the video stream was provided by the microprocessor. As the video data rate was high relative to the processor speed, the computer could only perform actual non-display computations during the retrace period between display frames. This limited performance to at most 25% of overall available CPU cycles.

These systems could thus build a very capable system with relatively few components, but the low transistor count of early programmable logic meant that the capabilities of early PLA-based systems were often less impressive than those using the video interface controllers or video coprocessors that were available at the same time. Later PLA solutions, such as those using [CPLD](/source/Complex_programmable_logic_device)s or [FPGAs](/source/Field-programmable_gate_array), could result in much more advanced video systems, surpassing those built using off-the-shelf components.

An often-used hybrid solution was to use a video interface controller (often the [Motorola 6845](/source/Motorola_6845)) as a basis and expand its capabilities with programmable logic or an [ASIC](/source/Application-specific_integrated_circuit). An example of such a hybrid solution is the original [VGA](/source/Video_Graphics_Array) card, that used a 6845 in combination with an ASIC. That is why all current VGA based video systems still use the [hardware register](/source/hardware_register)s that were provided by the 6845.

==Modern solutions==
[[File:Radeon R300 block diagram.svg|thumb|right|upright=1.9|[ATi R300 chip](/source/ATi_Radeon_R300_Series) block diagram. The display controller is labelled "display interface".]]

With the advancements made in [semiconductor device fabrication](/source/semiconductor_device_fabrication), more and more functionality is implemented as [integrated circuit](/source/integrated_circuit)s, often licensable as [semiconductor intellectual property core](/source/semiconductor_intellectual_property_core) (SIP core). Display controller [System In Package](/source/System_In_Package) (SiP) blocks can be found on the [die](/source/Die_(integrated_circuit)) of [GPUs](/source/Graphics_processing_unit), [APUs](/source/AMD_Accelerated_Processing_Unit) and [SoCs](/source/System_on_a_chip).{{Cn|date=December 2022}}

They support a variety of [interfaces](/source/interface_(computing)): [VGA](/source/Video_Graphics_Array), [DVI](/source/Digital_Visual_Interface), [HDMI](/source/HDMI), [DisplayPort](/source/DisplayPort), [VHDCI](/source/Very-high-density_cable_interconnect), [DMS-59](/source/DMS-59) and more. The [PHY](/source/PHY) includes [LVDS](/source/Low-voltage_differential_signaling), [Embedded DisplayPort](/source/Embedded_DisplayPort), [TMDS](/source/Transition-minimized_differential_signaling) and [Flat Panel Display Link](/source/Flat_Panel_Display_Link), [OpenLDI](/source/OpenLDI) and [CML](/source/Current-mode_logic).{{Cn|date=December 2022}} A modern [computer monitor](/source/computer_monitor) may has built-in LCD controller or OLED controller.<ref> https://www.xhpanel.com/info-detail/lcd-controller-boards-everything-you-need-to-know</ref>

For example, a VGA-signal, which is created by GPU is being transported over a VGA-cable to the monitor built-in controller. Both ends of the cable end in a [VGA connector](/source/VGA_connector). [Laptop](/source/Laptop)s and other [mobile computer](/source/mobile_computer)s use different interfaces between the display controller and the display. A display controller usually supports multiple [computer display standard](/source/computer_display_standard)s.

[KMS driver](/source/KMS_driver) is an example of a [device driver](/source/device_driver) for display controllers and [AMD Eyefinity](/source/AMD_Eyefinity) is a special brand of display controller with [multi-monitor](/source/multi-monitor) support.

[RandR](/source/RandR) (resize and rotate) is a method to configure screen resolution and refresh rate on each individual outputs separately and at the same time configure the settings of the windowing system accordingly.

An example for this dichotomy is offered by [ARM Holdings](/source/ARM_Holdings): they offer SIP core for 3D rendering acceleration and for display controller independently. The former has marketing names such as Mali-200 or Mali-T880 while the latter is available as Mali-DP500, Mali-DP550 and Mali-DP650.<ref>{{cite web |url=http://lkml.iu.edu/hypermail/linux/kernel/1604.0/00503.html |title=Initial support for ARM Mali Display Controller |publisher=[Linux kernel mailing list](/source/Linux_kernel_mailing_list) |date=2016-04-01}}</ref>

==History==
In 1982, [NEC](/source/NEC) released the [NEC μPD7220](/source/NEC_%CE%BCPD7220), one of the most widely used video display controllers in 1980s [personal computers](/source/personal_computer). It was used in the [NEC PC-9801](/source/NEC_PC-9801), [APC III](/source/APC_III), [IBM PC compatible](/source/IBM_PC_compatible)s, [DEC Rainbow](/source/DEC_Rainbow), [Tulip System-1](/source/Tulip_System-1), and [Epson QX-10](/source/Epson_QX-10).<ref>{{Cite web |title= Graphics with the NEC 7220: Direct access with Turbo Pascal |first= Guido |last= Dampf |date= 1986 |url= http://electrickery.xs4all.nl/comp/qx10/doc/Mc7220_summary.txt |access-date= 27 July 2013 |archive-date= 2 May 2019 |archive-url= https://web.archive.org/web/20190502004456/http://electrickery.xs4all.nl/comp/qx10/doc/Mc7220_summary.txt |url-status= dead }} (Translation of "Grafik mit dem 7220 von NEC", ''mc'', 1986, H11, pp. 54-65)</ref> [Intel](/source/Intel) licensed the design and called it the 82720 graphics display controller.<ref>{{Cite book |title= A graphics system design based on the INTEL 82720 graphics display controller |author= Changon Tsay |publisher= University of Texas at El Paso |work= Dissertation |date= January 1, 1986 |pages= 1–152 |url= http://digitalcommons.utep.edu/dissertations/AAIEP02441 }}</ref>

Previously, graphic cards were also called graphic adapters, and the chips used on these [ISA](/source/Industry_Standard_Architecture)/[EISA](/source/Extended_Industry_Standard_Architecture) cards consisted solely of a display controller, as this was the only functionality required to connect a computer to a display. Later cards included ICs to perform calculations related to 2D rendering in parallel with the CPU; these cards were referred to as graphics accelerator cards. Similarly, ICs for 3D rendering eventually followed. Such cards were available with [VLB](/source/VESA_Local_Bus), [PCI](/source/Peripheral_Component_Interconnect), and [AGP](/source/Accelerated_Graphics_Port) interfaces; modern cards typically use the [PCI Express](/source/PCI_Express) bus, as they require much greater bandwidth then the ISA bus can deliver.

==See also==
*[List of home computers by video hardware](/source/List_of_home_computers_by_video_hardware)
*[List of color palettes](/source/List_of_color_palettes)

==References==
{{Reflist}}

==External links==
* {{YouTube|Ja8fM7rTae4|Embedded Linux Conference 2013 – Anatomy of an Embedded KMS driver}} KMS driver is a device driver for display controllers

{{Graphics Processing Unit}}

Category:Graphics chips
Category:Television technology

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Adapted from the Wikipedia article [Video display controller](https://en.wikipedia.org/wiki/Video_display_controller) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Video_display_controller?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.