# Variable retention time

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{{Short description|DRAM reliability issue}}
{{About|the DRAM memory phenomenon|other uses|Variable retention (disambiguation){{!}}Variable retention}}
thumb|A DDR4 DRAM module
'''Variable retention time''' (also known as '''VRT''') is a reliability issue in [dynamic random-access memory](/source/dynamic_random-access_memory) (DRAM) characterized by unpredictable fluctuations in the retention time of [memory cells](/source/Memory_cell_(computing)), that is, the duration for which a cell can reliably store data without being [refreshed](/source/Memory_refresh).<ref>{{Cite book |last1=Restle |last2=Park |last3=Lloyd |title=International Technical Digest on Electron Devices Meeting |chapter=DRAM variable retention time |date=1992 |pages=807–810 |doi=10.1109/IEDM.1992.307481 |isbn=0-7803-0817-4 }}</ref> If a cell's retention time becomes shorter than the refresh interval, it may lead to memory errors, potentially resulting in [system crashes](/source/System_crash_screen) or [Silent data corruption](/source/Silent_data_corruption). VRT-affected bits that go undetected during [product testing](/source/Wafer_testing) may pose a significant risk to device reliability. To mitigate the impact of VRT<ref>{{Cite arXiv|title=Retrospective: An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms|author=Onur Mutlu|eprint=2306.16037|class=cs.AR|date=2023}}</ref> and [soft errors](/source/Soft_error), DRAM manufacturers have implemented [error-correcting code](/source/Error_correction_code) (ECC) mechanisms directly within the [memory chips](/source/Memory_chip). This approach has become a standard feature in [DDR5 SDRAM](/source/DDR5_SDRAM).<ref name=":6">{{cite web |date=July 2020 |title=JESD79-5: DDR5 SDRAM Standard |url=https://www.jedec.org/news/pressreleases/jedec-publishes-new-ddr5-standard-advancing-next-generation-high-performance |access-date=2025-07-07 |publisher=JEDEC Solid State Technology Association |quote=See page 243 for details on in-DRAM ECC}}</ref> 

Possible sources of VRT bits include high-voltage gate stress,<ref name=":0">{{Cite journal |last1=Kim |first1=Heesang |last2=Oh |first2=Byoungchan |last3=Kim |first3=Kyungdo |last4=Cha |first4=Seon-Yong |last5=Jeong |first5=Jae-Goan |last6=Hong |first6=Sung-Joo |last7=Lee |first7=Jong-Ho |last8=Park |first8=Byung-Gook |last9=Shin |first9=Hyungcheol |date=2010-09-01 |title=Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor |url=https://iopscience.iop.org/article/10.1143/JJAP.49.094102 |journal=Japanese Journal of Applied Physics |volume=49 |issue=9R |article-number=094102 |doi=10.1143/JJAP.49.094102 |bibcode=2010JaJAP..49i4102K |issn=0021-4922|url-access=subscription }}</ref> exposure to [high-energy particles radiation](/source/Cosmic_ray)<ref>{{Cite journal |last1=Goiffon |first1=Vincent |last2=Jay |first2=Antoine |last3=Paillet |first3=Philippe |last4=Bilba |first4=Teddy |last5=Deladerriere |first5=Theo |last6=Beaugendre |first6=Guillaume |last7=Le Roch |first7=Alexandre |last8=Dion |first8=Arnaud |last9=Virmontois |first9=Cedric |last10=Belloir |first10=Jean-Marc |last11=Gaillardin |first11=Marc |date=2020 |title=Radiation-Induced Variable Retention Time in Dynamic Random Access Memories |journal=IEEE Transactions on Nuclear Science |volume=67 |issue=1 |pages=234–244 |doi=10.1109/TNS.2019.2956293 |bibcode=2020ITNS...67..234G |issn=0018-9499 }}</ref> and high temperature stress.<ref name=":1">{{Cite book |last1=Kim |first1=Y.I. |last2=Yang |first2=K.H. |last3=Lee |first3=W.S. |chapter=Thermal degradation of DRAM retention time: Characterization and improving techniques |date=2004 |title=2004 IEEE International Reliability Physics Symposium. Proceedings |publisher= |pages=667–668 |doi=10.1109/RELPHY.2004.1315442 |isbn=978-0-7803-8315-9}}</ref>

== Background ==

{{also|Row hammer#Background}}
In dynamic random-access memory (DRAM), each [bit](/source/bit) of data is stored in a memory cell composed of a [capacitor](/source/capacitor) and a [transistor](/source/transistor). The amount of [electrical charge](/source/Electric_charge) stored in the capacitor determines whether the cell represents a binary "1" or "0". These cells are densely packed into integrated circuits, accompanied by [control logic](/source/control_logic) that manages data access. Due to the inherent leakage of charge from capacitors over time, DRAM cells must be periodically [refreshed](/source/Memory_refresh) to maintain data integrity this involves rewriting the contents of each cell at regular intervals to prevent [data loss](/source/data_loss).<ref name="ece548">{{cite web
| url = https://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf
| title = Understanding DRAM Operation
| date = December 1996
| access-date = March 10, 2015
| publisher = [IBM](/source/IBM)
| archive-url = https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf
| archive-date = August 29, 2017
}}</ref>

== Overview ==
thumb|In the case of data '1' retention, when the voltage on the storage capacitor reduces below a certain threshold, data corruption may occur.  Retention time (tRET) is set by the time required for reaching this condition.
The amount of time a cell can reliably store data without being [refreshed](/source/Memory_refresh) is called cell's retention time (<math>tRET</math>). In the case of a constant leakage current (<math>I_D</math>), <math>tRET</math> can be approximated as
{{center|1=<math>tRET\approx\frac{C\cdot \Delta V}{I_D}</math>,}}
where <math>C</math> is the storage node capacitance and <math>C\cdot \Delta V</math> is the amount of charge loss required in order to have a failure.<ref name=":8" /> In modern devices, at operating temperatures, <math>I_D</math> is dominated by [generation current](/source/Carrier_generation_and_recombination) due to defects in the cell's [access transistor](/source/Memory_cell_(computing)). Variability in defect configuration is responsible for a wide spread of the value of leakage current, and therefore of <math>tRET</math>, across different memory cells.<ref name=":3">{{Cite journal |last1=Liu |first1=Yong |last2=Wang |first2=Da |last3=Ren |first3=Pengpeng |last4=Li |first4=Jie |last5=Qiao |first5=Zheng |last6=Wu |first6=Maokun |last7=Wen |first7=Yichen |last8=Zhou |first8=Longda |last9=Sun |first9=Zixuan |last10=Wang |first10=Zirui |last11=Han |first11=Qinghua |last12=Wu |first12=Blacksmith |last13=Cao |first13=Kanyu |last14=Wang |first14=Runsheng |last15=Ji |first15=Zhigang |date=2024 |title=Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part I: Defect-Based Statistical Compact Model |journal=IEEE Transactions on Electron Devices |volume=71 |issue=8 |pages=4462–4468 |doi=10.1109/TED.2024.3409510 |bibcode=2024ITED...71.4462L |issn=0018-9383}}</ref>  

Only a few cells actually have <math>tRET</math> approaching the refresh interval.<ref name=":5">{{Cite journal |last1=Hiraiwa |first1=A. |last2=Ogasawara |first2=M. |last3=Natsuaki |first3=N. |last4=Itoh |first4=Y. |last5=Iwai |first5=H. |date=1996-09-01 |title=Statistical modeling of dynamic random access memory data retention characteristics |url=https://pubs.aip.org/jap/article/80/5/3091/494650/Statistical-modeling-of-dynamic-random-access |journal=Journal of Applied Physics |language=en |volume=80 |issue=5 |pages=3091–3099 |doi=10.1063/1.363119 |bibcode=1996JAP....80.3091H |issn=0021-8979|url-access=subscription }}</ref> To improve yield and reliability, DRAM chips include redundant [rows or columns](/source/Dynamic_random-access_memory) that can be used to replace faulty ones or single cells including those with retention times shorter than the refresh interval.<ref name=":2">{{Cite journal |last1=Cenker |first1=R.P. |last2=Clemons |first2=D.G. |last3=Huber |first3=W.R. |last4=Petrizzi |first4=J.B. |last5=Procyk |first5=F.J. |last6=Trout |first6=G.M. |date=1979 |title=A fault-tolerant 64K dynamic random-access memory |journal=IEEE Transactions on Electron Devices |volume=26 |issue=6 |pages=853–860 |doi=10.1109/T-ED.1979.19509 |bibcode=1979ITED...26..853C |issn=0018-9383}}</ref> However, this technique is less effective against VRT cells, which may begin to fail only after faulty cell replacement has been performed, typically at the [die](/source/Die_(integrated_circuit)) level.<ref name=":2" />

== Physics ==

{{multiple image
| align             = center
| total_width       = 600
| image1            = Link trap-energy leakage current defect silicon.svg
| alt1              = A donkey
| caption1          = Structural modification of the defect may alter its energy level
| image2            = Charge-state_model_of_VRT_diagram.svg
| alt2              = A trout
| caption2          = Electrical charge trapped in the gate-oxide may significantly affect electric field at the defect site
| footer            = Physical models for VRT
}}

At the microscopic level, defects located in the bulk or at the Si/[SiO<sub>2</sub>](/source/Silicon_dioxide) interface of the access transistor are believed to be the primary source of leakage responsible for the discharge of the storage capacitor.<ref name=":3" /> According to [Shockley–Read–Hall (SRH) theory](/source/Carrier_generation_and_recombination), the [generation](/source/Carrier_generation_and_recombination) rate depends on trap [energy level](/source/energy_level) (<math>E_T</math>), free [carrier concentration](/source/Charge_carrier_density), and temperature.<ref>{{Cite journal |last1=Shockley |first1=W. |last2=Read |first2=W. T. |date=1952-09-01 |title=Statistics of the Recombinations of Holes and Electrons |url=https://link.aps.org/doi/10.1103/PhysRev.87.835 |journal=Physical Review |volume=87 |issue=5 |pages=835–842 |doi=10.1103/PhysRev.87.835 |bibcode=1952PhRv...87..835S |url-access=subscription }}</ref> In the case of defects located in the depleted region, where free carrier concentrations are typically negligible and the generation rate is maximized, the current can be approximated as: 
{{center|1=<math>I_{SRH} \simeq \frac{q n_i \sigma v_{th}}{2 \cosh \left( \frac{|E_T-E_i|}{kT}\right)}</math>,}} 
where <math>E_i</math> is the intrinsic [Fermi energy](/source/Band_diagram), <math>n_i</math> is the [intrinsic carrier concentration](/source/Charge_carrier_density) in silicon, <math>\sigma</math> is the capture [cross section](/source/Cross_section_(physics)) which determines the probability of carrier capture and emission (assumed to be equal for electrons and holes for simplicity), <math>v_{th}</math> is the thermal velocity of carriers.<ref name=":5" /> Large [electric fields](/source/Electric_field)(<math>F</math>) are known to enhance <math>\sigma</math>,  resulting in increased generation current. Incorporating this effect, the total leakage current can be expressed as
{{center|1=<math>I=(1+\Gamma (F,E_T) )\cdot I_{SRH}(E_T)</math>,}} 
where <math>\Gamma(F,E_T)</math> is the field enhancement factor, a positive quantity that becomes significant under strong electric fields.<ref>{{Cite journal |last1=Hurkx |first1=G.A.M. |last2=Klaassen |first2=D.B.M. |last3=Knuvers |first3=M.P.G. |date=1992 |title=A new recombination model for device simulation including tunneling |journal= IEEE Transactions on Electron Devices|volume=39 |issue=2 |pages=331–338 |doi=10.1109/16.121690 |bibcode=1992ITED...39..331H |issn=1557-9646}}</ref>

Generation current may fluctuate over time displaying a [random telegraph noise (RTN)](/source/Burst_noise) pattern,<ref>{{Cite book |last1=Mori |first1=Y. |last2=Ohyu |first2=K. |last3=Okonogi |first3=K. |last4=Yamada |first4=R.-i. |title=IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest |chapter=The origin of variable retention time in DRAM |date=2005 |publisher= |pages=1034–1037 |doi=10.1109/IEDM.2005.1609541 |isbn=978-0-7803-9268-7}}</ref> with [transition rates](/source/Transition-rate_matrix) having an [Arrhenius](/source/Arrhenius_equation) dependence on temperature. To explain the origin of these instabilities, two main theoretical models have been proposed. One model attributes VRT to structural modifications of the defect, which cause changes in the trap energy level.<ref name=":4" /> The other model suggests that VRT arises from modulation of the local electric field, attributed to changes in the [charge state](/source/Electric_charge) of nearby defects, often located in the [gate oxide](/source/gate_oxide).<ref>{{Cite journal |last1=Oh |first1=Byoungchan |last2=Cho |first2=Heung-Jae |last3=Kim |first3=Heesang |last4=Son |first4=Younghwan |last5=Kang |first5=Taewook |last6=Park |first6=Sunyoung |last7=Jang |first7=Seunghyun |last8=Lee |first8=Jong-Ho |last9=Shin |first9=Hyungcheol |date=2011 |title=Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors |journal=IEEE Transactions on Electron Devices |volume=58 |issue=6 |pages=1741–1747 |doi=10.1109/TED.2011.2126046 |bibcode=2011ITED...58.1741O |issn=1557-9646}}</ref><ref>{{Cite journal |last1=Mori |first1=Yuki |last2=Yoshimoto |first2=Hiroyuki |last3=Takeda |first3=Kenichi |last4=Yamada |first4=Ren-ichi |date=2012-05-29 |title=Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor |journal=Journal of Applied Physics |volume=111 |issue=10 |pages=104513–104513–9 |doi=10.1063/1.4721658 |bibcode=2012JAP...111j4513M |issn=0021-8979}}</ref> Both models have been supported by experimental evidence,<ref>{{Cite journal |last1=Mori |first1=Yuki |last2=Yoshimoto |first2=Hiroyuki |last3=Takeda |first3=Kenichi |last4=Yamada |first4=Ren-ichi |date=2012-05-29 |title=Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor |journal=Journal of Applied Physics |volume=111 |issue=10 |pages=104513–104513–9 |doi=10.1063/1.4721658 |bibcode=2012JAP...111j4513M |issn=0021-8979}}</ref><ref name=":4">{{Cite book |last1=Ohyu |first1=K. |last2=Umeda |first2=T. |last3=Okonogi |first3=K. |last4=Tsukada |first4=S. |last5=Hidaka |first5=M. |last6=Fujieda |first6=S. |last7=Mochizuki |first7=Y. |chapter=Quantitative identification for the physical origin of variable retention time: A vacancy-oxygen complex defect model |date=2006 |title=2006 International Electron Devices Meeting |pages=1–4 |doi=10.1109/IEDM.2006.346792 |isbn=1-4244-0438-X }}</ref> suggesting that the VRT may originate from different physical phenomena.<ref>{{Cite journal |last1=Kim |first1=Heesang |last2=Oh |first2=Byoungchan |last3=Son |first3=Younghwan |last4=Kim |first4=Kyungdo |last5=Cha |first5=Seon-Yong |last6=Jeong |first6=Jae-Goan |last7=Hong |first7=Sung-Joo |last8=Shin |first8=Hyungcheol |date=2011 |title=Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM |journal=  IEEE Transactions on Electron Devices|volume=58 |issue=6 |pages=1643–1648 |doi=10.1109/TED.2011.2125964 |bibcode=2011ITED...58.1643K |issn=1557-9646}}</ref>

== Mitigation ==
Considerable effort has been spent to mitigate the effects of VRT, including modifications to the fabrication process and the introduction of error correction mechanisms.<ref name=":7" /><ref name=":9" />  

=== Screening and in-DRAM ECC ===
{{also|ECC memory}}
{{also|DDR5 SDRAM#Features}}

There are no efficient mechanisms to screen VRT bits during [production testing](/source/Wafer_testing). Most manufacturers have been able to deal with it by increasing average retention time and by enforcing larger test screen margins, involving the replacement of possibly faulty cells with spare rows and columns.<ref name=":8">{{Cite journal |last=Kang |first=Uksong |date=2014 |title=Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling |journal=The Memory Forum 2014 |s2cid=14770136 }}</ref> However, starting from [sub-20nm node](/source/Semiconductor_device_fabrication) it became increasingly costly to screen and manage the growing number of defective cells, due to the sharply increasing area overhead required to fit adequate redundant resources.<ref name=":7">{{Cite book |last1=Cha |first1=Sanguhn |last2=Seongil |first2=O. |last3=Shin |first3=Hyunsung |last4=Hwang |first4=Sangjoon |last5=Park |first5=Kwangil |last6=Jang |first6=Seong Jin |last7=Choi |first7=Joo Sun |last8=Jin |first8=Gyo Young |last9=Son |first9=Young Hoon |last10=Cho |first10=Hyunyoon |last11=Ahn |first11=Jung Ho |last12=Kim |first12=Nam Sung |title=2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) |chapter=Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices |date=2017 |publisher=IEEE |pages=61–72 |doi=10.1109/HPCA.2017.30 |isbn=978-1-5090-4985-1}}</ref> 

In-DRAM [ECC](/source/Error_correction_code), coupled with traditional redundant sparing, was identified as the most effective solution,<ref name=":7" /> and became a [JEDEC standard](/source/JEDEC_memory_standards) for [DDR5 SDRAM](/source/DDR5_SDRAM).<ref name=":6" /> This technique involve dividing memory data into codewords and encode information adding extra parity bits, to enable the detection and correction of errors. This provides the ability to address faulty bits that were not identified as such during testing, such as VRT ones.<ref name=":7" />  

The key difference with the more traditional [ECC DRAM](/source/ECC_memory) lies in where the extra bits are stored. In in-DRAM ECC, parity bits are stored in the same chip, and error correction occurs internally to the chip, making it transparent to the [memory controller](/source/memory_controller). In ECC DRAM an extra chip is added to the DIMM to store the extra bits information, providing detection and correction of data transfer errors.<ref>{{Cite web |date=10 July 2025 |title=ECC Technical Details |url=https://www.memtest86.com/ecc.htm |access-date=10 July 2025 |website=[memtest86](/source/memtest86)}}</ref>

=== Physical treatments ===
Researchers have investigated [passivation](/source/Semiconductor_device_fabrication) strategies to reduce the number of active defects in the silicon. Researchers have shown that [hydrogen](/source/hydrogen) [anneal](/source/Annealing_(materials_science)) at high temperature strongly reduces VRT,<ref name=":1" /> as confirmed by later experiments that highlighted a correlation with the reduction of charge pumping current, a metric typically used to assess the defect density at the Si/[SiO<sub>2</sub>](/source/Silicon_dioxide)  interface in [MOSFETs](/source/MOSFET).<ref>{{Cite book |last1=Ryu |first1=Seong-Wan |last2=Min |first2=Kyungkyu |last3=Shin |first3=Jungho |last4=Kwon |first4=Heimi |last5=Nam |first5=Donghoon |last6=Oh |first6=Taekyung |last7=Jang |first7=Tae-Su |last8=Yoo |first8=Minsoo |last9=Kim |first9=Yongtaik |last10=Hong |first10=Sungjoo |title=2017 IEEE International Electron Devices Meeting (IEDM) |chapter=Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing |date=2017 |publisher=IEEE |pages=21.6.1–21.6.4 |doi=10.1109/IEDM.2017.8268437 |isbn=978-1-5386-3559-9}}</ref>
  
[Fluorine](/source/Fluorine) implantation was reported to reduce VRT in older technologies.<ref name=":4" /> This method was later observed to reduce the number of cells with gate-induced drain leakage, current that is a [leakage](/source/Leakage_(semiconductors)) mechanism induced by the presence of large electric fields at the gate drain overlap region of MOSFETs.<ref>{{Cite journal |last1=Weber |first1=A. |last2=Birner |first2=A. |last3=Krautschneider |first3=W. |date=2007-11-01 |title=DRAM retention tail improvement by trap passivation |url=https://www.sciencedirect.com/science/article/pii/S0038110107003218 |journal=Solid-State Electronics |series=Special Issue: Papers Selected from the 36th European Solid-State Device Research Conference - ESSDERC'06 |volume=51 |issue=11 |pages=1534–1539 |doi=10.1016/j.sse.2007.09.023 |bibcode=2007SSEle..51.1534W |issn=0038-1101|url-access=subscription }}</ref> [Samsung](/source/Samsung_Electronics) researchers found that the number of VRT errors can be reduced by changes in the [process steps](/source/Semiconductor_device_fabrication) for the formation of the metal gate in a [1znm process](/source/Semiconductor_device_fabrication).<ref name=":9">{{Cite journal |last1=Jang |first1=Dongkyu |last2=Kim |first2=Daekyum |last3=Lee |first3=Jieun |last4=Lee |first4=Inkyum |last5=Ahn |first5=Sang Bin |last6=Hong |first6=Yoonki |last7=Kim |first7=Shindeuk |last8=Park |first8=Taehoon |last9=Ban |first9=Hyodong |date=2024-06-01 |title=Improvement of VRT immunity using low 10-boron word line in recent DRAM |url=https://www.sciencedirect.com/science/article/pii/S0026271424000763 |journal=Microelectronics Reliability |volume=157 |article-number=115396 |doi=10.1016/j.microrel.2024.115396 |bibcode=2024MiRe..15715396J |issn=0026-2714|url-access=subscription }}</ref> 

== See also ==

* [Soft error](/source/Soft_error) {{snd}} A type of error involving changes to signals or data but no changes to the underlying device or circuit
* [ECC](/source/Error_correction_code) {{snd}} Scheme for controlling errors in data over noisy communication channels
* [Row hammer](/source/Row_hammer) {{snd}} A computer exploit that takes advantage of unintended and undesirable side-effect in DRAM
== References ==
<references />
== External links ==
* [https://www.synopsys.com/articles/ecc-memory-error-correction.html Error correction Code (ECC) in DDR Memories], Oct 19, 2020, by Vadhiraj Sankaranarayanan
* [https://www.memtest86.com/ecc.htm ECC Technical Details]
* [https://www.atpinc.com/tw/blog/ddr5-what-is-on-die-ecc-how-is-it-different-to-traditional-ecc DDR5: What is On-Die ECC?], Aug 7, 2023
* [https://siliconvlsi.com/what-is-gidlgate-induced-drain-leakage-in-mosfet/ Gate Induced Drain Leakage – An Overview] Jan 18, 2022, By siliconvlsi
Category:Synchronous dynamic random-access memory
Category:Semiconductor properties
Category:MOSFETs
Category:Nanoelectronics

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Adapted from the Wikipedia article [Variable retention time](https://en.wikipedia.org/wiki/Variable_retention_time) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Variable_retention_time?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.