# Test register > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Test_register > Markdown URL: https://mediated.wiki/source/Test_register.md > Source: https://en.wikipedia.org/wiki/Test_register > Source revision: 1341469217 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) A '''test register''', in the [Intel 80386](/source/Intel_80386) and [Intel 80486](/source/Intel_80486) processors, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named '''TR3''' to '''TR7'''. Regular programs don't usually require these registers to work. With the [Pentium](/source/P5_(microarchitecture)), the test registers were replaced by a variety of [model-specific register](/source/model-specific_register)s (MSRs).Intel, [https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241428-005.pdf Pentium® Processor Family Developer’s Manual], order no. 241428-005, 1997, section 16.1.2, page 442 - provides a list of Pentium MSRs that provide the same functionality as the 386/486 TRx registers. In the 80386, two test registers, '''TR6''' and '''TR7''', were provided for the purpose of [TLB](/source/Translation_lookaside_buffer) testing. TR6 was the test command register, and TR7 was the test data register. The 80486 provided three additional registers, '''TR3''', '''TR4''' and '''TR5''', for testing of the L1 cache. TR3 was a data register, TR4 was an address register and TR5 was a command register. These registers were accessed by variants of the [MOV](/source/MOV_(x86_instruction)) instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both [real-address mode](/source/real-address_mode) and [protected mode](/source/protected_mode). The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at [privilege level](/source/privilege_level) 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on most CPUs newer than 80486. The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as 0F 26 /r (with r/m being the GPR, and reg being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as 0F 24 /r (with r/m being the GPR, and reg being the test register).{{Cite book|url=https://manualzz.com/doc/51363286/intel-dj-equipment-80386-user-manual|title=Introduction to the 80386 Including the 80386 Data Sheet|date=April 1986|publisher=[Intel](/source/Intel)|pages=122}} Only register-register moves are supported - as such, the "mod" field (top 2 bits) of the instruction's [ModR/M](/source/ModR%2FM) byte should be set to 11b. (Setting the "mod" field of the ModR/M byte to anything else than 11b results in undefined behaviour, with different behaviour observed on different processors.Robert L. Hummel, [https://archive.org/details/pc-magazine-programmers-technical-reference-1992/ PC Magazine Programmer's Technical Reference], 1992, {{ISBN|1-56276-016-5}}, page 476.) The test registers and/or associated opcodes were supported in the following [x86](/source/x86) processors: {| class="wikitable" |- ! rowspan="2" | Processors !! colspan="3" {{n/a}} !! colspan="3" | Cache Test Registers !! colspan="2" | TLB Test Registers |- ! TR0 !! TR1 !! TR2 !! TR3 !! TR4 !! TR5 !! TR6 !! TR7 |- | Intel 386 (all models) || colspan="3" {{no}} || colspan="1" {{no}} || colspan="2" {{maybe|undoc{{efn|On the Intel 386, the TR4 and TR5 registers have been reported to act as undocumented read-only registers returning a data item related to instruction prefetch.Robert Collins, [https://web.archive.org/web/19970605213647/http://www.x86.org/secrets/MoveSpecial.html Move Special Registers], archived on 5 Jun 1997.}}}} || colspan="2" {{yes}} |- | Intel 486 (all models) || colspan="3" {{no}} || colspan="3" {{yes}} || colspan="2" {{yes}} |- | [AMD 386](/source/Am386) (all models)
AMD Élan SC3xx || colspan="3" {{no}} || {{no}} || colspan="2" {{dunno}} || colspan="2" {{yes|YesAMD, [http://www.bitsavers.org/components/amd/x86/1992_AM386_Microprocessors_for_Personal_Computers.pdf Am386 Microprocessors Data Book], 1992, pages 21 and 151}} |- | [AMD 486](/source/Am486) (all models)
[AMD 5x86](/source/Am5x86)
AMD Élan SC4xx,SC5xx || colspan="3" {{no}} || colspan="3" {{yes|YesAMD, [https://www.amd.com/system/files/TechDocs/18497.pdf Am486® Microprocessor Software User’s Manual], rev.1, 1994, section 1.59, p. 82}} || colspan="2" {{yes}} |- | [IBM 386SLC](/source/IBM_386SLC)
IBM BL486SLC2/SX2/SX3 || colspan="3" {{no}} || colspan="3" {{yes|YesJohn H. Wharton, [https://bitsavers.org/pdf/microDesign/Microdesign_-_The_Complete_X86_Volume_1_1994.pdf The Complete X86, Volume 1], 1994. ''MicroDesign Resources'', {{ISBN|1-885330-02-2}}, page 296.}} || colspan="2" {{yes}} |- | [C&T](/source/Chips_and_Technologies) Super386 || colspan="3" {{no}} || colspan="3" {{no}} || colspan="2" {{yes|YesChips and Technologies, [https://bitsavers.org/components/chipsAndTech/050085-001_CHIPS_Super386_DX_Programmers_Manual_Preliminary_1992.pdf Super386 DX Programmer's Reference Manual], {{nowrap|pub.no. UG85,}} rev 1.0, 1992, page 201.}} |- | [NexGen](/source/NexGen) Nx586 || colspan="3" {{no}} || colspan="3" {{no}} || colspan="2" {{yes|YesNexGen, [https://www.ardent-tool.com/CPU/docs/NexGen/db001_00.pdf Nx586™ Processor and Nx587™ Numerics Processor Databook], 8 July 1993, page 116}} |- | [Cyrix](/source/Cyrix){{efn|text=[Cyrix manufacturing partner](/source/Cyrix) CPU models from [IBM](/source/IBM), [TI](/source/Texas_Instruments) and [ST](/source/STMicroelectronics) also all supported the same test registers as their corresponding Cyrix-branded CPU models.}} 486 (all models{{efn|SoCs based on the Cyrix-derived ST486 CPU core also supported the same set of test registers as the Cyrix 486 - such SoCs include e.g. STPC Atlas and ZFMicro ZFx86.ZFMicro, [http://www.zfmicro.com/library/manuals/ZFx86_Data_Book.pdf ZFx86 Data Book 1.0 Rev D], 5 June 2006, page 101}}) || colspan="3" {{no}} || colspan="3" {{yes|YesCyrix, [http://www.bitsavers.org/components/cyrix/Cyrix_Cx486DLC_Data_Sheet_May92.pdf Cx486DLC Microprocessor Data Sheet], order no. 94706-01, May 1992, section 2.3.2.6, p.37}} || colspan="2" {{yes}} |- | [Cyrix 5x86](/source/Cyrix_5x86) || {{no}} || colspan="2" {{maybe|undocSandpile, [https://web.archive.org/web/20110520212942/http://sandpile.org/ia32/ccr.htm IA32 Configuration Control Registers], see the BTB_TR bit in registers 20h and 30h for how to enable the undocumented TR1/TR2 registers on Cyrix 5x86, 6x86 and 6x86MX. Archived from the [http://sandpile.org/ia32/ccr.htm original] on 20 May 2011.}} || colspan="3" {{yes}} || colspan="2" {{yes}} |- | [Cyrix 6x86](/source/Cyrix_6x86) || {{no}} || colspan="2" {{maybe|undoc{{efn|On the Cyrix 6x86, the TR1 and TR2 registers could be enabled by setting bit 6 of Cyrix configuration register 30h. These registers are not documented, but example code using them has been published by Cyrix.Cyrix, [https://www.ardent-tool.com/CPU/docs/Cyrix/6x86/bios.pdf 6x86 BIOS Writer’s Guide], revision 4.1, 29 July 1996, page 43.}}}} || colspan="3" {{yes}} || colspan="2" {{yes|Yes (VSPM){{efn|On the Cyrix 6x86, the TR6 and TR7 registers could be used not only to test the TLB, but also to configure the processor's VSPM (Variable-Size Paging Mechanism).Cyrix, [https://www.ardent-tool.com/CPU/docs/Cyrix/6x86/94175.pdf 6x86 Processor data book], order no. 94175-01, March 1996, section 2.6.5, p. 74 The VSPM was a 4-entryLinux kernel archive, [https://lkml.iu.edu/hypermail/linux/kernel/9611.0/0308.html Re: Cyrix 6x86 Patch..], 4 Nov 1996 software TLB with a per-entry mask to support all power-of-2 page sizes from 2^{12} to 2^{32} bytes. It was present in the Cyrix 6x86 only - it was removed in 6x86MX and later processors.}}}} |- | Cyrix 6x86MX, MII|| {{no}} || colspan="2" {{maybe|undoc}} || colspan="3" {{yes|Yes (scratchpad){{efn|name=m2_scratch|text=On the 6x86MX, MII, and "Joshua" Cyrix III processors, the TR3-TR5 registers could be used not just to test the L1 cache but also to lock individual L1 cache-lines to specific addresses for [scratchpad memory](/source/scratchpad_memory) use.Cyrix, [https://www.ardent-tool.com/CPU/docs/Cyrix/6x86MX/94329.pdf 6x86MX Processor Data Book], order no. 94329-00, 15 July 1997, section 2.13.1.1, page 87VIA-Cyrix Corp., [http://datasheets.chipdb.org/VIA/Joshua/cyrix3db.pdf Cyrix III Processor Data Book], v1.0, 25 January 2000, section 2.9.1.1, page 86}}}} || colspan="2" {{yes}} |- | VIA [Cyrix III](/source/Cyrix_III){{efn|"Joshua" core only. "Samuel" core variants of Cyrix III did not support the TRx test registers.}} || {{no}} || colspan="2" {{dunno}} || colspan="3" {{yes|Yes (scratchpad){{efn|name=m2_scratch}}}} || colspan="2" {{yes}} |- | Cyrix [MediaGX](/source/MediaGX)
[NatSemi](/source/National_Semiconductor) [Geode GX](/source/Geode_(processor)) || {{no}} || colspan="2" {{dunno}} || colspan="3" {{yes|YesCyrix, [http://datasheets.chipdb.org/Cyrix/MediaGX/gxmdb_v20.pdf MediaGX Processor Data Book], rev 2.0, 29 October 1998, section 3.3.2.4, p.59}} || colspan="2" {{yes}} |- | NatSemi Geode GX2
AMD Geode GX, LX || colspan="8" {{maybe|align="left"|TR0-TR7 registers present as 32-bit read/write data registers
without any cache/TLB test functionality.AMD, [https://www.amd.com/system/files/TechDocs/33234H_LX_databook.pdf Geode™ LX Processors Data Book], publication ID: 33234H, February 2009, section 8.3.4.3, p.648}} |- | IDT [WinChip](/source/WinChip) (all models) || colspan="8" {{maybe|align="left"|Registers not present. The MOV TRx opcodes can be enabled
with the WinChip's FCR.EMOVTRIDT, [http://datasheets.chipdb.org/IDT/x86/C6/c6_data_sheet.pdf WinChip C6 Processor Data Sheet], section A.2, p.79 bit, but will act as NOPs.}} |- | [Intel Quark](/source/Intel_Quark) X1000 || colspan="3" {{no}} || colspan="3" {{yes|YesIntel, [https://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf Quark SOC X1000 Core Developer's Manual], order no. 329679-001, October 2013, appendix B, page 296}} || colspan="2" {{yes}} |} {{notelist}} ==See also== *[Control register](/source/Control_register) *[x86 debug register](/source/x86_debug_register) ==References== {{Reflist}} {{DEFAULTSORT:Test register}} Category:Digital registers Category:X86 architecture {{Microcompu-stub}} --- Adapted from the Wikipedia article [Test register](https://en.wikipedia.org/wiki/Test_register) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Test_register?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.