# SystemRDL

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Language to describe control status registers

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The **SystemRDL** language, supported by the [SPIRIT Consortium](/source/SPIRIT_Consortium), was specifically designed to describe and implement a wide variety of [control status registers](/source/Control_Status_Register). Using SystemRDL, developers can automatically generate and synchronize register views for specification, hardware design, software development, verification, and documentation.

SystemRDL is an open source text based descriptive language that focuses exclusively on registers. SystemRDL 1.0 had some limitations and is now superseded by SystemRDL 2.0 which has support for verification based properties like constraints, coverage, and HDL paths. SystemRDL 2.0 also introduces the ability to parameterize components which further improves design re-use.

## See also

- [SystemVerilog](/source/SystemVerilog)

- [SystemC](/source/SystemC)

- [IP-XACT](/source/IP-XACT)

## Companies/tools

- Commercial - Agnisys [1] - Semifore's CSR Compiler[2] - Magillem [3]

- Open Source - Open Register Design Tool released by [Juniper Networks](/source/Juniper_Networks) under Apache 2.0 open source license[4] - SystemRDL compiler at [GitHub](/source/GitHub) supports SystemRDL 2.0 and generators for documentation and [IP-XACT](/source/IP-XACT).[5]

## References

1. **[^](#cite_ref-1)** [Agnisys IDesignSpec](https://www.agnisys.com/products/idesignspec-uvm-register-generator/)

1. **[^](#cite_ref-2)** [Semifore's CSR Compiler](http://semifore.com/csrcompiler/)

1. **[^](#cite_ref-3)** [Magillem system-rdl](http://blog.magillem.com/system-rdl)

1. **[^](#cite_ref-4)** [Open Register Design Tool](https://github.com/Juniper/open-register-design-tool)

1. **[^](#cite_ref-5)** [github.com SystemRDL compiler](https://github.com/SystemRDL)

## External links

- [SystemRDL](https://www.accellera.org/downloads/standards/systemrdl) Accellera Standards

- [SystemRDL Alliance](https://www.denali.com/en/partners/rdl.jsp)

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