# SuperH

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Instruction set architecture by Hitachi

SuperH (SH) Designer Hitachi Bits 32-bit (32 → 64) Introduced 1992[1] Design RISC Encoding SH-2: 16-bit instructions SH-2A and newer: mixed 16- and 32-bit instructions Endianness Bi Open Yes, and royalty-free[2] (reverse-engineered after patents expired)

**SuperH** (or **SH**) is a [32-bit](/source/32-bit) [reduced instruction set computing](/source/Reduced_instruction_set_computing) (RISC) [instruction set architecture](/source/Instruction_set_architecture) (ISA) developed by [Hitachi](/source/Hitachi) and currently produced by [Renesas](/source/Renesas). It is implemented by [microcontrollers](/source/Microcontroller) and [microprocessors](/source/Microprocessor) for [embedded systems](/source/Embedded_system).

At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the [register file](/source/Processor_register) was smaller and instructions were generally two-operand format. However, for the market the SuperH was aimed at, this was a small price to pay for the improved memory and [processor cache](/source/Processor_cache) efficiency.

Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the [machine code](/source/Machine_code) to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a [compressed instruction set](/source/Compressed_instruction_set) and is also used by other companies, the most notable examples being [ARM](/source/ARM_architecture) for its [Thumb](/source/ARM_architecture#Thumb) instruction set, along with [RISC-V](/source/RISC-V) for its compressed extensions.

In 2015, many of the original [patents](/source/Patent) for the SuperH architecture expired and the SH-2 CPU was reimplemented as [open source hardware](/source/Open_source_hardware) under the name [J2](#J_Core).

## History

### SH-1 and SH-2

SH-2 on Sega 32X and Sega Saturn

The SuperH processor core family was first developed by [Hitachi](/source/Hitachi) in the early 1990s. The design concept was for a single [instruction set](/source/Instruction_set) (ISA) that would be [upward compatible](/source/Upward_compatible) across a series of [CPU cores](/source/CPU_core).

In the past, this sort of design problem would have been solved using [microcode](/source/Microcode), with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.

One of the key realizations during the development of the [RISC](/source/RISC) concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported MUL, DMULS and DMULU, whereas the SH-1 would cause a trap if these were encountered.[3]

The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.[3] The SH-1 and the SH-2 were used in the [Sega Saturn](/source/Sega_Saturn), [Sega 32X](/source/Sega_32X) and [Capcom CPS-3](/source/Capcom_CPS-3).[4]

The ISA uses [16-bit](/source/16-bit) instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of [main memory](/source/DRAM) and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.[5]

Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one [delay slot](/source/Delay_slot).[6]

### SH-3

A few years later, the SH-3 core was added to the family; new features included another [interrupt](/source/Interrupt) concept, a [memory management unit](/source/Memory_management_unit) (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.[3] The SH-3 was [bi-endian](/source/Endianness#Bi-endian_hardware), running in either big-endian or little-endian byte ordering.

The SH-3 core also added a [DSP](/source/Digital_signal_processing) extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated [MAC](/source/Multiply%E2%80%93accumulate)-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core. It was used in [Microsoft](/source/Microsoft)'s [Pocket PC](/source/Pocket_PC) cellphone line.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.[7]

### SH-4

In 1997, Hitachi and [STMicroelectronics](/source/STMicroelectronics) (STM) started collaborating on the design of the SH-4 for the [Dreamcast](/source/Dreamcast). SH-4 featured [superscalar](/source/Superscalar) (2-way) instruction execution and a [vector](/source/Vector_processor) [floating-point unit](/source/Floating-point_unit) (particularly suited to [3D graphics](/source/3D_graphics)). Standard chips based on the SH-4 were introduced around 1998.[8]

### Licensing

In early 2001, Hitachi and STM formed the [IP company](/source/Patent_holding_company) SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.[8][9]

In 2003, Hitachi and [Mitsubishi Electric](/source/Mitsubishi_Electric) formed a joint-venture called [Renesas Technology](/source/Renesas_Electronics), with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.[10] Renesas Technology later became Renesas Electronics, following their merger with [NEC Electronics](/source/NEC_Electronics).

The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and [SIMD](/source/Single_instruction%2C_multiple_data) instructions. In SHmedia mode the destination of a [branch](/source/Branch_(computer_science)) (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; [ARM](/source/ARM_architecture) processors have a 16-bit [Thumb](/source/ARM_architecture#Thumb) mode (ARM licensed several patents from SuperH for Thumb[11]) and [MIPS](/source/MIPS_architecture) processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for [symmetric multiprocessing](/source/Symmetric_multiprocessing).

### Continued availability

Since 2010, the SuperH CPU cores, architecture, and product designs are owned by [Renesas Electronics](/source/Renesas_Electronics), with the architecture consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms.

Renesas's system-on-chip products originally based on SH-3, SH-4, and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from [Arm Ltd.](/source/Arm_Ltd.), though many of the existing models continued to be marketed and sold until March 2025 through the Renesas Product Longevity Program.[12]

As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including [Arm](/source/Arm_architecture), [RX](/source/RX_microcontroller_family), and [RH850](/source/V850).

### J Core

Not to be confused with [Samsung Galaxy J2 Core](/source/Samsung_Galaxy_J2_Core).

The last of the SH-2 patents expired in 2014. At [LinuxCon](/source/LinuxCon) Japan 2015, j-core developers presented a [cleanroom reimplemention](/source/Clean_room_design) of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired [trademarks](/source/Trademarks)).[11][13] Subsequently, a design walkthrough was presented at ELC 2016.[14]

The [open source](/source/Open-source_license) [BSD](/source/Berkeley_Software_Distribution)-licensed [VHDL](/source/VHDL) code for the J2 core has been proven on [Xilinx](/source/Xilinx) [FPGAs](/source/FPGA) and on [ASICs](/source/ASIC) manufactured on [TSMC](/source/TSMC)'s [180 nm](/source/180_nm) process, and is capable of booting [μClinux](/source/%CE%9CClinux).[11] J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016–2017.[11][*[needs update](https://en.wikipedia.org/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items)*]

Several features of SuperH have been cited as motivations for designing new cores based on this architecture:[11]

- High [code density](/source/Code_density) compared to other 32-bit [RISC](/source/RISC) [ISAs](/source/Instruction_set_architecture) such as [ARM](/source/ARM_architecture) or [MIPS](/source/MIPS_architecture)[15] important for cache and memory bandwidth performance

- Existing [compiler](/source/C_compiler) and [operating system](/source/Operating_system) support ([Linux](/source/Linux), [Windows Embedded](/source/Windows_Embedded), [QNX](/source/QNX)[13])

- Extremely low ASIC [fabrication](/source/Semiconductor_fabrication) costs now that the patents are expiring (around US$0.03 for a dual-core J2 core on TSMC's 180 nm process).

- Patent- and royalty-free (BSD-licensed) implementation

- Full and vibrant[*[clarification needed](https://en.wikipedia.org/wiki/Wikipedia:Please_clarify)*] community support

- Availability of low cost hardware development platform for zero cost FPGA tools

- CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation

- Clean, modern design[*[citation needed](https://en.wikipedia.org/wiki/Wikipedia:Citation_needed)*] with open source design, generation, simulation and verification environment

## Models

Generation comparison[16] Clock [MHz] Computer performance Image MIPS MOPS GFLOPS SH-1 20 20 SH-2 28,7 78 120 SH-3 200 260 400 SH-4 200 480 1,9 SH-5 400 700 9600 2,8 SH-6 >2000 >24000 >7,0

The family of SuperH CPU cores includes:

- SH-1 – used in microcontrollers for deeply embedded applications ([CD-ROM](/source/CD-ROM) drives, [major appliances](/source/Major_appliance), etc.)

- SH-2 – used in microcontrollers with higher performance requirements, networking applications, and also in video game consoles, like the [Sega Saturn](/source/Sega_Saturn) and [Sega 32X](/source/Sega_32X) add-on. The SH-2 has also found home in many automotive [engine control unit](/source/Engine_control_unit) applications, including [Subaru](/source/Subaru), [Mitsubishi](/source/Mitsubishi_Motors), and [Mazda](/source/Mazda).

- SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation

- SH-DSP – initially developed for the [mobile phone](/source/Mobile_phone) market, used later in many consumer applications requiring DSP performance for [JPEG](/source/JPEG) compression etc.

- SH-3 – used for mobile and handheld applications such as the [Jornada](/source/Jornada_(PDA)), strong in [Windows CE](/source/Windows_CE) applications and market for many years in the car navigation market. The [Cave CV1000](/source/Arcade_system_board#Cave), similar to the [Sega NAOMI](/source/Sega_NAOMI) hardware's CPU, also made use of this CPU. The Korg Electribe EMX and ESX music production units also use the SH-3.[17]

- SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines

- SH-4 – used whenever high performance is required such as car multimedia terminals, [video game consoles](/source/Video_game_console), most notably the [Dreamcast](/source/Dreamcast), or [set-top boxes](/source/Set-top_box)

- SH-5 – used in high-end 64-bit multimedia applications

- SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones

- SH-Mobile – SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI

### SH-2

Hitachi SH-2 CPU (bottom-right, with colored stripes on it)

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware [multiply–accumulate](/source/Multiply%E2%80%93accumulate) (MAC) block for DSP algorithms and has a five-stage pipeline.

The SH-2 has a cache on all [ROM](/source/Read-only_memory)-less devices.

It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register.

Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.

### SH-2A

The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.

New features on the SH-2A core include:

- Superscalar architecture: execution of 2 instructions simultaneously

- [Harvard architecture](/source/Harvard_architecture)

- Two 5-stage pipelines

- Mixed 16-bit and 32-bit instructions

- 15 register banks for interrupt response in 6 cycles.

- Optional FPU

The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as [CAN](/source/Controller-area_network), [Ethernet](/source/Ethernet), [USB](/source/USB) and more as well as more application-specific peripherals such as [motor control](/source/Motor_controller) timers, [TFT](/source/Thin-film_transistor) controllers and peripherals dedicated to automotive powertrain applications.

### SH-3

Hitachi SH-3 CPU ([BGA](/source/Ball_grid_array) version)

### SH-4

The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's [Dreamcast](/source/Dreamcast) and [NAOMI](/source/List_of_Sega_arcade_system_boards#Sega_Naomi) game systems. It includes a much more powerful floating-point unit[\[note\]](#endnote_casio) and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.

SH-4 features include:

- FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats

- 4D floating-point [dot-product operation](/source/Dot-product_operation) and [matrix–vector multiplication](/source/Matrix%E2%80%93vector_multiplication)

- 128-bit floating-point bus allowing 3.2 GB/sec transfer rate from the data cache

- 64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4 GB addressable memory (see [Byte addressing](/source/Byte_addressing)) with a transfer rate of 800 MB/sec

- Built-in interrupt, DMA, and power management controllers

**[^](#ref_casio)**There is no FPU in the custom SH-4 made for Casio, the SH7305, but it does have the DSP instruction set extension instead.

### SH-5

The SH-5 is a 64-bit RISC CPU.[18]

Almost no non-simulated SH-5 hardware was ever released,[19] and, unlike the still-live SH-4, support for SH-5 was dropped from [GCC](/source/GNU_Compiler_Collection)[20] and Linux.

### SH-6

SH-6 was an announced-but-never-implemented further development. It was supposed to achieve over 2 GIPS, over 7 GFLOPS and over 24 GOPS.[16]

## References

### Citations

1. **[^](#cite_ref-1)** ["The Story of the Hitachi SH-2 and the Sega Saturn"](https://web.archive.org/web/20230227165625/https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn). *www.sega-16.com*. Renesas. Archived from [the original](https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn) on 2023-02-27. Retrieved 27 February 2023.

1. **[^](#cite_ref-2)** [J-core Open Processor](http://j-core.org)

1. ^ [***a***](#cite_ref-FOOTNOTEProgram19961_3-0) [***b***](#cite_ref-FOOTNOTEProgram19961_3-1) [***c***](#cite_ref-FOOTNOTEProgram19961_3-2) [Program 1996](#CITEREFProgram1996), p. 1.

1. **[^](#cite_ref-4)** ["CP System III (CPS3) Hardware (Capcom)"](https://www.system16.com/hardware.php?id=799). *www.system16.com*. System 16. Retrieved 3 August 2019.

1. **[^](#cite_ref-FOOTNOTEProgram199630–33_5-0)** [Program 1996](#CITEREFProgram1996), pp. 30–33.

1. **[^](#cite_ref-6)** ["SH7020 and SH7021 Hardware ManualSuperH™ RISC engine"](https://www.renesas.com/us/en/document/mah/superh-risc-engine-sh7020-and-sh7021-hd6437020-hd6477021-hd6437021-hd6417021?r=469371). p. 19,48. Retrieved 2023-12-02.

1. **[^](#cite_ref-7)** ["360-MIPS SuperH RISC Processor Enables Personal Access Systems SH7750 Launches the SH-4 Series"](https://web.archive.org/web/20160305103423/http://segatech.com/technical/cpu/tech_sh4.html). November 1997. Archived from [the original](http://segatech.com/technical/cpu/tech_sh4.html) on 5 March 2016.

1. ^ [***a***](#cite_ref-sh5_8-0) [***b***](#cite_ref-sh5_8-1) ["STMicro, Hitachi plan new company to develop RISC cores"](http://www.eetimes.com/document.asp?doc_id=1180485). *EE Times*. 3 April 2001. Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.

1. **[^](#cite_ref-9)** ["SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH Cores in Embedded Microprocessor Applications"](http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682).{{[cite web](https://en.wikipedia.org/wiki/Template:Cite_web)}}: CS1 maint: deprecated archival service ([link](https://en.wikipedia.org/wiki/Category:CS1_maint:_deprecated_archival_service))

1. **[^](#cite_ref-10)** Clarke, Peter (28 September 2004). ["Renesas to take over SuperH core business"](https://www.eetimes.com/renesas-to-take-over-superh-core-business/). *EE Times*.

1. ^ [***a***](#cite_ref-lwn_11-0) [***b***](#cite_ref-lwn_11-1) [***c***](#cite_ref-lwn_11-2) [***d***](#cite_ref-lwn_11-3) [***e***](#cite_ref-lwn_11-4) Nathan Willis (June 10, 2015). ["Resurrecting the SuperH architecture"](http://lwn.net/Articles/647636). [LWN.net](/source/LWN.net).

1. **[^](#cite_ref-12)** [""SuperH RISC Engine Family MCUs""](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/other-mcus-mpus/superh-risc-engine-family-mcus). *Renesas Electronics*.

1. ^ [***a***](#cite_ref-0pf_jcore_13-0) [***b***](#cite_ref-0pf_jcore_13-1) ["J Cores"](https://web.archive.org/web/20160511092659/http://j-core.org/). j-core. Archived from [the original](http://j-core.org) on May 11, 2016. Retrieved April 27, 2016.

1. **[^](#cite_ref-14)** ["j-core Design Walkthrough"](http://j-core.org/talks/ELC-2016.pdf) (PDF). [Archived](https://web.archive.org/web/20160617085346/http://j-core.org/talks/ELC-2016.pdf) (PDF) from the original on 2016-06-17.

1. **[^](#cite_ref-weaver2015_15-0)** V.M. Weaver (17 March 2015). ["Exploring the Limits of Code Density (Tech Report with Newest Results)"](http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf) (PDF). [Archived](https://web.archive.org/web/20150713143728/http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf) (PDF) from the original on 2015-07-13.

1. ^ [***a***](#cite_ref-FumioArakawa_16-0) [***b***](#cite_ref-FumioArakawa_16-1) Fumio Arakawa (2013-07-27). ["SH-5: A First 64-bit SuperH Core with Multimedia Extension"](https://old.hotchips.org/wp-content/uploads/hc_archives/hc13/2_Mon/05hitachi.pdf) (PDF; 617 kB). Hitachi, Ltd. Retrieved 2022-02-08.

1. **[^](#cite_ref-17)** Kuwabara, M. (25 July 2019). ["Korg EMX / ESX Service Manual"](https://web.archive.org/web/20190713235231/http://dealers.korgusa.com/svcfiles/ESX1_Svc_%20man.pdf) (PDF). Archived from [the original](http://dealers.korgusa.com/svcfiles/ESX1_Svc_%20man.pdf) (PDF) on 13 July 2019.

1. **[^](#cite_ref-18)** ["SH-5 CPU Core, Volume1: Architecture"](http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf) (PDF). [Archived](https://web.archive.org/web/20090320050543/http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf) (PDF) from the original on 2009-03-20.

1. **[^](#cite_ref-19)** ["Wasabi SH-5 Press Release"](http://www.bsdnewsletter.com/2002/10/News47.html). 8 March 2016.

1. **[^](#cite_ref-20)** ["GCC 7 Release Series Changes, New Features, and Fixes"](https://gcc.gnu.org/gcc-7/changes.html). 2 February 2018.

### Bibliography

- [*SuperH RISC Engine SH-1/SH-2 Programming Manual*](https://antime.kapsi.fi/sega/files/h12p0.pdf) (PDF). Hitachi Americal Ltd. 3 September 1996. Retrieved 2020-12-06.

- [*SH-4 CPU Core Architecture*](http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00147165.pdf) (PDF). STMicroelectronics and Hitachi Ltd. 12 September 2002. ADCS 7182230F. Retrieved 2020-12-06.

## External links

- [Renesas SuperH](https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/superh.html), Products, Tools, Manuals, App.Notes, Information

- [J-core Open Processor](http://j-core.org)

- [J-core](https://github.com/j-core) on [GitHub](/source/GitHub)

- [Linux SuperH development list](https://lore.kernel.org/linux-sh/)

- [DCTP - Hitachi 200 MHz SH-4](https://web.archive.org/web/20160810170747/http://segatech.com/technical/cpu/index.html) at the [Wayback Machine](/source/Wayback_Machine) (archived August 10, 2016)

- [in-progress Debian port for SH4](http://wiki.debian.org/SH4)

- Chen, Raymond (5 August 2019). ["The SuperH-3, part 1: Introduction"](https://devblogs.microsoft.com/oldnewthing/20190805-00/?p=102749). *The Old New Thing* (blog). Retrieved 2024-01-22. A 15-part series on programming for the microprocessor.

v t e Renesas Electronics Products RL78 RX RH850 SuperH V850 78K R8C R8C Tiny M32R H8 740 IEBus

v t e Hitachi Divisions and subsidiaries Current GlobalLogic Hitachi Cable Hitachi Cable Manchester Hitachi Canadian Industries Hitachi Capital Hitachi Construction Machinery Bradken Hitachi Construction Machinery (Europe) Hitachi Consulting Hitachi Data Systems (BlueArc) Hitachi eBworx Hitachi Electronics Hitachi Energy Hitachi Medical Systems Hitachi Rail Hitachi Rail STS Hitachi Rail Italy Horizon Nuclear Power JECS Former Clarion Euclid Trucks1 Fabrik1 Hitachi Global Storage Technologies2 Maxell Joint ventures and shareholdings Current GE Vernova Hitachi Nuclear Energy (40%) Astemo (19%) Keihin Nissin Showa Tokico Hitachi-LG Data Storage Johnson Controls-Hitachi Air Conditioning (40%) Tata Hitachi Construction Machinery (60%) Former Agility Trains Alaxala Networks Japan Display Casio Hitachi Mobile Communications Nippon Columbia Renesas Electronics Products, services and standards Current ALiS EMIEW Adaptable Modular Storage 2000 Hitachi Starboard Locomotives Hitachi Magic Wand Multiple units Hitachi 917 Hitachi SR8000 Hitachi TrueCopy LS-R M8 Stacked Volumetric Optical Disk SuperH Universal Storage Platform Defunct D-VHS H8 Family HD64180 HITAC HITAC S-810 Hitachi 6309 Deskstar Hitachi Flora Prius Hitachi G1000 Hitachi Hatsukaze Hitachi SR2201 Hitachi T.2 Hitachi TR.1 M6 Microdrive Travelstar People Namihei Odaira Kenichi Ohmae Hiroaki Nakanishi Takashi Kawamura Places Hitachi Kashiwa Soccer Stadium Hitachi, Ibaraki Hitachi Tower Tsūtenkaku Other DKB Group HDMI Licensing Hitachi 3Tours Championship Hitachi Data Systems History The Hitachi Foundation Hitachi Sundiva Hitachi SunRockers Hitachi Rivale Kashiwa Reysol 1Now integrated into other Hitachi divisions or business groupings 2Sold to Western Digital Category Commons

v t e Reduced instruction set computer (RISC) architectures Origins IBM 801 Berkeley RISC Stanford MIPS Development active Analog Devices Blackfin ARC ARM AVR eSi-RISC LatticeMico8, LatticeMico32 MIPS OpenRISC Power ISA Renesas M32R, SuperH, V850 RISC-V LoongISA LoongArch SPARC Sunway Unicore Xilinx MicroBlaze, PicoBlaze Development discontinued Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CR16 CRISP DEC PRISM Intel i860, i960 META MIPS-X Motorola 88000, M·CORE PA-RISC ROMP

v t e Processor technologies Models Abstract machine Stored-program computer Finite-state machine with datapath Hierarchical Deterministic finite automaton Queue automaton Cellular automaton Quantum cellular automaton Turing machine Alternating Turing machine Universal Post–Turing Quantum Nondeterministic Turing machine Probabilistic Turing machine Hypercomputation Zeno machine Belt machine Stack machine Register machines Counter Pointer Random-access Random-access stored program Architecture Microarchitecture Von Neumann Harvard modified Dataflow Transport-triggered Cellular Endianness Memory access NUMA HUMA Load–store Register/memory Cache hierarchy Memory hierarchy Virtual memory Secondary storage Heterogeneous Fabric Multiprocessing Cognitive Neuromorphic Instruction set architectures Types Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes Instruction sets Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False sharing Out-of-order Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue Speculative Branch prediction Memory dependence prediction Parallelism Level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed Multithreading Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD Processor performance Transistor count Instructions per cycle (IPC) Cycles per instruction (CPI) Instructions per second (IPS) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic updates per second (SUPS) Performance per watt (PPW) Cache performance metrics Computer performance by orders of magnitude Types Central processing unit (CPU) Graphics processing unit (GPU) GPGPU Vector Barrel Stream Tile processor Coprocessor PAL ASIC FPGA FPOA CPLD Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP) By application Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor Systems on chip System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC) Hardware accelerators Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor Word size 1-bit 4-bit 8-bit 12-bit 15-bit 16-bit 24-bit 32-bit 48-bit 64-bit 128-bit 256-bit 512-bit bit slicing others variable Core count Single-core Multi-core Manycore Heterogeneous architecture Components Core Cache CPU cache Scratchpad memory Data cache Instruction cache replacement policies coherence Bus Clock rate Clock signal FIFO Functional units Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder Logic Combinational Sequential Glue Logic gate Quantum Array Registers Processor register Status register Stack register Register file Memory buffer Memory address register Program counter Control unit Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter Datapath Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter Circuitry Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch Power management PMU APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Performance per watt (PPW) Related History of general-purpose CPUs Microprocessor chronology Processor design Digital electronics Hardware security module Semiconductor device fabrication Tick–tock model Pin grid array Chip carrier

v t e Instruction set extensions SIMD (RISC) Alpha MVI ARM NEON SVE MIPS MDMX MIPS-3D MXU MIPS SIMD PA-RISC MAX Power ISA VMX SPARC VIS SIMD (x86) MMX (1996) 3DNow! (1998) SSE (1999) SSE2 (2001) SSE3 (2004) SSSE3 (2006) SSE4 (2006) SSE5 (2007) AVX (2008) F16C (2009) XOP (2009) FMA (FMA4: 2011, FMA3: 2012) AVX2 (2013) AVX-512 (2015) AMX (2022) AVX10 (2023) Bit manipulation BMI (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012) ADX (2014) Compressed instructions Thumb MIPS16e ASE RVC Security and cryptography PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory TSX (2013) ASF Virtualization VT-x (2005) AMD-V (2006) AMD-Vi / VT-d (2011) General-purpose registers AMD64 (1999) APX (2023) Suspended extensions' dates are struck through.

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Adapted from the Wikipedia article [SuperH](https://en.wikipedia.org/wiki/SuperH) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/SuperH?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.