# Stream Processors, Inc. > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Stream_Processors%2C_Inc. > Markdown URL: https://mediated.wiki/source/Stream_Processors%2C_Inc..md > Source: https://en.wikipedia.org/wiki/Stream_Processors%2C_Inc. > Source revision: 1257771206 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) {{More citations needed|date=December 2023}} {{Infobox company | name = Stream Processors, Inc. |logo = 106px|SPI logo |type=[Private](/source/Private_company) | foundation = 2004 | location= [Sunnyvale, California](/source/Sunnyvale%2C_California), [United States](/source/United_States) | key_people =[Bill Dally](/source/Bill_Dally), Co-Founder and ex-Chairman | num_employees = Approximately 100 (2007) | industry =[Semiconductors](/source/Semiconductors)-Specialized | products= [Digital Signal Processor](/source/Digital_Signal_Processor) | homepage=[http://www.streamprocessors.com/ www.streamprocessors.com] }} '''Stream Processors, Inc.''' ('''SPI'''), was a [Silicon Valley](/source/Silicon_Valley)–based [fabless semiconductor company](/source/fabless_semiconductor_company) specializing in the design and manufacture of high-performance [digital signal processor](/source/digital_signal_processor)s for applications including [video surveillance](/source/video_surveillance), [multi-function printers](/source/multi-function_printer) and [video conferencing](/source/video_conferencing). The company ceased operations in 2009. ==Company history== Foundational work in [stream processing](/source/stream_processing) was initiated in 1995 by a research team led by [MIT](/source/MIT) professor [Bill Dally](/source/Bill_Dally). In 1996, he moved to [Stanford University](/source/Stanford_University) where he continued this work, receiving a multimillion-dollar grant from [DARPA](/source/DARPA) with additional resources from [Intel](/source/Intel) and [Texas Instruments](/source/Texas_Instruments) to fund the development of a project called "Imagine" - the first stream processor chip and accompanying [compiler](/source/compiler) tools. ===The Imagine Project=== The goal of the Imagine project was to develop a [C](/source/C_(programming_language))-programmable signal and image processor intended to provide both the performance density and efficiency of a special-purpose processor (such as a hard-wired [ASIC](/source/ASIC)). The project successfully demonstrated the advantages of stream processing. Details on the Imagine project and its results are posted on [http://cva.stanford.edu/projects/imagine/ the Stanford Imagine project page]. The work also showed that a number of applications ranging from wireless [baseband](/source/baseband) processing, 3D graphics, [encryption](/source/encryption), [IP forwarding](/source/IP_forwarding) to video processing could take advantage of the efficiency of stream processing. This research inspired other designs such as [GPU](/source/GPU)s from [ATI Technologies](/source/ATI_Technologies) as well as the [Cell microprocessor](/source/Cell_microprocessor) from [Sony](/source/Sony), [Toshiba](/source/Toshiba), and [IBM](/source/IBM). The main deliverables from the Imagine program included: * The Imagine Stream Architecture * The Stream programming model * Software development tools * Programmable graphics and real-time media applications * [VLSI](/source/VLSI) prototype (fabricated by TI) * Stream processor development platform (a prototype development board) ===SPI established=== Dally, together with other team members, obtained a license from Stanford to commercialize the resulting technology. Stream Processors, Incorporated (SPI) was incorporated in California in 2004. Professor Dally remained at Stanford and the company hired industry veteran Chip Stearns to become the President and CEO in December of that year.[http://www.streamprocessors.com/streamprocessors/Home/About/PressReleases/2004-12-13.html Press release] streamprocessors.com December 13, 2004 Through June, 2006 SPI has been able to raise a total of $26M from a trio of notable [venture capital](/source/venture_capital) firms – [Austin Ventures](/source/Austin_Ventures), [Norwest Venture Partners](/source/Norwest_Venture_Partners) and the Woodside Fund. The company launched its first two products concurrently with the International Solid State Circuits Conference ([ISSCC](/source/ISSCC)) in February, 2006[http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197005077 EETimes.com - Startup touts stream processing architecture for DSPs] and has introduced two others since.{{Cite web|url=http://www.videsignline.com/shared/article/showArticle.jhtml?articleId=198702004 |title=Data-parallel DSP aimed at cost-sensitive video surveillance apps | Video Imaging DesignLine|accessdate=18 December 2023}}[http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=199701328 EETimes.com - Stream Processors claims fastest DSP] SPI has headquarters located in [Sunnyvale, California](/source/Sunnyvale%2C_California), as well as a software development group (SPI Software Technologies Pvt. Ltd) located in [Bangalore, India](/source/Bangalore%2C_India). In January 2009 Co-Founder Prof. [Bill Dally](/source/Bill_Dally) accepted a position as Chief Scientist with [NVIDIA](/source/NVIDIA) Corporation.{{Cite web|url=http://www.nvidia.com/object/io_1233142016114.html|title = Home}} At the same time he resigned as chairman.{{Cite web|url=https://venturebeat.com/2009/05/22/interview-stanfords-bill-dally-leaps-from-academia-to-the-computer-graphics-wars/|title = Stanford's Bill Dally leaps from academia to the computer graphics wars|date = 22 May 2009}} In an interview Dally reflected on his experiences with startups: " I have done several chip startups myself. It’s getting hard. The ante is very high. If you do a chip startup, you need patient investors with very deep pockets. It’s many tens of millions of dollars to get to a first product and $50 million to get to profits. That’s very difficult to do because investors want an exit some multiple over that investment. I am hoping we return to the days of frequent [IPO](/source/IPO)s and get beyond the fire-sale acquisitions. That’s not what you can see right now. If it’s a programmable chip, the cost is even more." In the summer of 2009 CEO Stearns left the company and was replaced by Mike Fister, an executive with senior level experience at [Cadence Design Systems](/source/Cadence_Design_Systems) and [Intel](/source/Intel). In September 2009 the company ceased operations.{{cite news|work=Silicon Valley Business Journal |url=http://sanjose.bizjournals.com/sanjose/stories/2009/11/02/daily124.html|title=Report: Chip startup Stream Processors to shut down |date=November 2, 2009|via=bizjournals.com}} ==Technology== Similar to graphics and scientific computing, media and signal processing are characterized by available data-parallelism, locality and a high computation to global memory access ratio. [Stream processing](/source/Stream_processing) exploits these characteristics using data-[parallel processing](/source/parallel_computing) fed by a [distributed memory](/source/distributed_memory) hierarchy managed by the compiler. The main challenge for next generation massively parallel processors is data bandwidth, not computational resources. Unlike most conventional processors, the technology does not rely on a [hardware cache](/source/hardware_cache) – instead data movement is explicitly managed by the compiler and hardware. The execution model is based on accelerating performance-critical functions (kernels) that process and produce data records (streams). Kernels and streams are scheduled at compile-time and moved to on-chip memory at runtime via a scoreboard. The compiler analyses data live times of streams to optimize allocation and minimize external memory bandwidth needs. Streams and kernels loads can overlap with execution to improve latency tolerance and the explicit data movement provides predictable performance. There are no [CPU cache](/source/CPU_cache) misses and the design presents a single-core model to the programmer – data-parallelism is within the kernels. ===Architecture=== The architecture includes a host [CPU](/source/CPU) (System MIPS) for system-level tasks and a DSP Coprocessor Subsystem where the DSP MIPS runs the main threads that make kernel [function call](/source/function_call)s to the Data Parallel Unit (DPU). For users that use libraries, and don't intend to develop DSP code, the architecture is a [MIPS](/source/MIPS_architecture)-based [system-on-a-chip](/source/system-on-a-chip) with an [API](/source/API) to a “black box” [coprocessor](/source/coprocessor). The DPU Dispatcher receives kernel function calls to manage runtime kernel and stream loads. One kernel at a time is executed across the lanes, operating on local stream data stored in the Lane Register File of each lane. Each lane has a set of [VLIW](/source/VLIW) [ALU](/source/Arithmetic_logic_unit)s and distributed operand register files (ORF) allow for a large working data set and processing bandwidth exceeding 1 TeraByte/s. The Stream Load/Store Unit provides gather/scatter with a wide variety of access patterns. The InterLane Switch is a [compiler](/source/compiler)-scheduled, full crossbar for high-speed access between lanes. ===Tools=== SPI's RapiDev Tools Suite leverages the predictability of [stream processing](/source/stream_processing) to provide a fast path to optimized results using [C programming](/source/C_programming). Starting with C reference code, the Fast Functional Debugger (FFD) library plugs into standard tools, such as [Microsoft Visual Studio](/source/Microsoft_Visual_Studio) and [GNU](/source/GNU), and simulates the DPU to support re-structuring code to kernels and streams. Because kernels are statically scheduled and data movement is explicit, DPU cycle-accuracy can be obtained even at this functional high level. This is one source of the predictability of the architecture. For targeting code to the device, the Stream Processor Compiler (SPC) generates the VLIW executable and [pre-processed](/source/preprocessor) C code that is compiled/[linked](/source/Linker_(computing)) via standard [GCC](/source/GNU_Compiler_Collection) for MIPS. SPC allocates streams in the Lane Register Files and provides [dependency](/source/Coupling_(computer_programming)) information for the kernel function calls. [Software pipelining](/source/Software_pipelining) and [loop unrolling](/source/loop_unrolling) are supported. Branch penalties are avoided by predicated selects and larger conditionals use conditional streams. Running under Eclipse, the Target Code Simulator provides comprehensive Host or Device binary code simulation with breakpoint and single-stepping capabilities with bandwidth and load statistics. A kernel view shows the VLIW pipeline for kernel optimizations, and a stream view shows kernel execution and stream loads to review global data movement for system profiling. ===Products=== SPI currently markets its Storm-1 family, that includes four fully software programmable DSPs of varying performance levels. {|class="wikitable" |- !Product !GMACS* !Applications |- valign="top" |SP16HP-G220 |224 | * Broadcasting/[transcoding](/source/transcoding) * Wireless Infrastructure |- valign="top" |SP16-G160 |160 | * Telepresence * Surveillance DVRs |- valign="top" |SP8-G80 |80 | * Printers, Scanners and MFPs * Surveillance DVRs |- valign="top" |SP8LP-G30 |32 | * Professional camcorder * IP Camera |} Note: GMACS stands for Giga (billions of) Multiply-Accumulate operations per Second, a common measure of DSP performance. ===Support hardware and software=== * The RapiDev tools suite delivers a fast, predictable path to optimized results, eliminating the complexities of assembly coding or manual cache management * The Storm-1 DevKit is a PCI-based software development platform * IP Camera Reference Design runs standard [Linux 2.6](/source/Linux_2.6) and supports multiple simultaneous [codec](/source/codec)s (e.g. [H.264](/source/H.264), [MPEG-4](/source/MPEG-4) and [MJPEG](/source/MJPEG)), arbitrary resolutions, [CMOS](/source/CMOS_sensor) and [CCD](/source/charge-coupled_device) sensor processing as well as [video analytics](/source/video_analytics) in a fully software-programmable platform * Video Streamer Reference Design supports eight [4CIF](/source/4CIF) input channels of video [compressed](/source/data_compression) to [H.264](/source/H.264) and a [Gigabit Ethernet](/source/Gigabit_Ethernet) output ==References== {{Reflist}} ==External links== * [http://cva.stanford.edu/projects/imagine/ The Imagine Project (Stanford) website] {{Coord|37|22|59.48|N|122|04|42.08|W|type:landmark_region:US-CA|display=title}} Category:Fabless semiconductor companies Category:Electronics companies established in 2004 Category:Companies based in Sunnyvale, California Category:Defunct semiconductor companies of the United States Category:Defunct computer companies of the United States Category:Defunct computer hardware companies --- Adapted from the Wikipedia article [Stream Processors, Inc.](https://en.wikipedia.org/wiki/Stream_Processors%2C_Inc.) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Stream_Processors%2C_Inc.?action=history)). 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