# SmartSpice

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{{notability|org|date=July 2023}}
'''SmartSpice''' is a commercial version of [SPICE](/source/SPICE) (Simulation Program with Integrated Circuit Emphasis) developed by [Silvaco](/source/Silvaco). SmartSpice is used to design complex [analog circuit](/source/analog_circuit)s, analyze critical nets, characterize cell libraries, and verify analog mixed-signal designs. SmartSpice is compatible with popular analog design flows and foundry-supplied device models. It supports a reduced design space simulation environment.<ref>{{cite web
 | title=Rounding Up Design Corners
 | url=http://chipdesignmag.com/sld/blog/2010/03/25/rounding-up-design-corners/
 | last=Chatterjee
 | first=Pallab
 | accessdate=2010-04-14
 | publisher=Chip Design Mag
}}</ref> Among its usages in the [electronics industry](/source/electronics_industry) is [dynamic timing analysis](/source/dynamic_timing_analysis).<ref name="DTA">{{cite book | title=CPU Design: Answers to Frequently Asked Questions | url=https://archive.org/details/cpudesignanswers00thim_0 | url-access=registration | publisher=Springer | author=Thimmannagari, Chandra | year=2005 | pages=[https://archive.org/details/cpudesignanswers00thim_0/page/201 201] | isbn=038723800X}}</ref>

==Key features==

* [HSPICE](/source/HSPICE)-compatible netlists, models, analysis features, and results
* Can handle up to 400,000 active devices in 32-bit and 8 million active devices in 64-bit version
* Supports multiple threads for parallel operation
* Multiple solvers and stepping algorithms
* Collection of calibrated SPICE models for traditional technologies (bipolar, CMOS) and emerging technologies (e.g., TFT, SOI,<ref name="SOI">{{cite book | title=SOI Design | publisher=Springer | author=Marshall, Andrew | author2=Natarajan, Sreedhar | year=2002 | pages=71}}</ref> HBT, FRAM) 
* Provides an open model development environment and analog behavioral capability with [Verilog-A](/source/Verilog-A) option
* Supports the [Cadence](/source/Cadence_Design) analog flow through OASIS
* Offers a transient non-[Monte Carlo method](/source/Monte_Carlo_method) to simulate the transient noise in nonlinear dynamic circuits

==Supported transistor models==
*'''BJT/HBT:''' 	Gummel-Poon, Quasi-RC, VBIC, MEXTRAM, MODELLA, HiCUM
*'''MOSFET:''' 	LEVEL 1, LEVEL 2, LEVEL 3, BSIM1, BSIM3, BSIM4, BSIM5, MOS 11, PSP, MOS 20, [EKV](/source/EKV_MOSFET_Model), HiSIM, HVMOS
*'''TFT:''' 	Amorphous and Polysilicon TFT models: Berkeley, Leroux, RPI
*'''SOI:''' 	Berkeley BSIM3SOI PD/DD/FD, UFS, LETISOI
*'''MESFET:''' 	Statz, Curtice I & II, TriQuint
*'''JFET:''' 	LEVEL 1, LEVEL 2
*'''Diode:''' 	Berkeley, Fowler-Nordheim, Philips JUNCAP/Level 500
*'''FRAM:''' 	[Ramtron](/source/Ramtron) FCAP

==Supported input formats==
Berkeley SPICE netlist, HSPICE netlist, W-element RLGC matrix files, S-parameter model files, Verilog-A and AMS, C/C++
 
==Supported output formats==
Rawfiles, output listings, Analysis results, Measurement data, Waveforms (portable across unix/windows platforms)

==References==
<references/>
==External links==
*[http://www.silvaco.com Silvaco]
*[http://www.silvaco.com/products/circuit_simulation/smartspice.html SmartSpice]

Category:Electronic design automation software
Category:Electronic circuit simulators

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Adapted from the Wikipedia article [SmartSpice](https://en.wikipedia.org/wiki/SmartSpice) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/SmartSpice?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.