# Single instruction, multiple data

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"SIMD" redirects here. For the cryptographic hash function, see [SIMD (hash function)](/source/SIMD_(hash_function)). For the Scottish statistical tool, see [Scottish index of multiple deprivation](/source/Scottish_index_of_multiple_deprivation).

See also: [SIMD within a register](/source/SIMD_within_a_register) and [Single instruction, multiple threads](/source/Single_instruction,_multiple_threads)

**Single instruction, multiple data** (**SIMD**) is a type of [parallel computing](/source/Parallel_computing) (processing) in [Flynn's taxonomy](/source/Flynn's_taxonomy). SIMD describes computers with [multiple processing elements](/source/Multiple_processing_elements) that perform the same operation on multiple data points simultaneously. SIMD can be internal (part of the hardware design) and it can be directly accessible through an [instruction set architecture](/source/Instruction_set_architecture) (ISA), but it should not be confused with an ISA.

Such machines exploit [data level parallelism](/source/Data_parallelism), but not [concurrency](/source/Concurrent_computing): there are simultaneous (parallel) computations, but each unit performs exactly the same instruction at any given moment (just with different data). A simple example is to add many pairs of numbers together, all of the SIMD units are performing an addition, but each one has different pairs of values to add. SIMD is especially applicable to common tasks such as adjusting the contrast in a [digital image](/source/Digital_image) or adjusting the volume of [digital audio](/source/Digital_audio). Most modern [central processing unit](/source/Central_processing_unit) (CPU) designs include SIMD instructions to improve the performance of [multimedia](/source/Multimedia) use. In recent CPUs, SIMD units are tightly coupled with cache hierarchies and prefetch mechanisms, which minimize latency during large block operations. For instance, AVX-512-enabled processors can prefetch entire cache lines and apply fused multiply-add operations (FMA) in a single SIMD cycle.

## Confusion between SIMT and SIMD

See also: [SIMD within a register](/source/SIMD_within_a_register), [Single instruction, multiple threads](/source/Single_instruction,_multiple_threads) and [Vector processor](/source/Vector_processor)

SIMD has three different subcategories in [Flynn's 1972 Taxonomy](/source/Flynn's_taxonomy#Single_instruction_stream,_multiple_data_streams_(SIMD)), one of which is [single instruction, multiple threads](/source/Single_instruction,_multiple_threads) (SIMT). SIMT should not be confused with [software threads](/source/Thread_(computing)) or [hardware threads](/source/Multithreading_(computer_architecture)), both of which are task time-sharing (time-slicing). SIMT is true simultaneous parallel hardware-level execution, such as in the [ILLIAC IV](/source/ILLIAC_IV).

SIMD should not be confused with [Vector processing](/source/Vector_processing), characterized by the [Cray 1](/source/Cray_1) and clarified in [Duncan's taxonomy](/source/Duncan's_taxonomy). The [difference between SIMD and vector processors](/source/Vector_processor#Difference_between_SIMD_and_vector_processors) is primarily the presence of a Cray-style SET VECTOR LENGTH instruction.

## History

The first known operational use to date of [SIMD within a register](/source/SIMD_within_a_register) was the [TX-2](/source/TX-2), in 1958. It was capable of 36-bit operations and two 18-bit or four 9-bit sub-word operations.

The first commercial use of SIMD instructions was in the [ILLIAC IV](/source/ILLIAC_IV), which was completed in 1972.

[Vector supercomputers](/source/Vector_processor) of the early 1970s such as the [CDC Star-100](/source/CDC_STAR-100) and the [Texas Instruments ASC](/source/TI_Advanced_Scientific_Computer) could operate on a "vector" of data with a single instruction. Vector processing was especially popularized by [Cray](/source/Cray) in the 1970s and 1980s. Vector processing architectures are now considered separate from SIMD computers: [Duncan's Taxonomy](/source/Duncan's_Taxonomy) includes them whereas [Flynn's Taxonomy](/source/Flynn's_Taxonomy) does not, due to Flynn's work (1966, 1972) pre-dating the [Cray-1](/source/Cray-1) (1977). The complexity of Vector processors however inspired a simpler arrangement known as [SIMD within a register](/source/SIMD_within_a_register).

The first era of modern SIMD computers was characterized by [massively parallel processing](/source/Massively_parallel_processing)-style [supercomputers](/source/Supercomputer) such as the [Thinking Machines](/source/Thinking_Machines_Corporation) [Connection Machine](/source/Connection_Machine) CM-1 and CM-2. These computers had many limited-functionality processors that would work in parallel. For example, each of 65,536 single-bit processors in a Thinking Machines CM-2 would execute the same instruction at the same time, allowing, for instance, to logically combine 65,536 pairs of bits at a time, using a hypercube-connected network or processor-dedicated RAM to find its operands. Supercomputing moved away from the SIMD approach when inexpensive scalar [multiple instruction, multiple data](/source/Multiple_instruction,_multiple_data) (MIMD) approaches based on commodity processors such as the [Intel i860 XP](/source/Intel_i860) became more powerful, and interest in SIMD waned.[1]

The current era of SIMD processors grew out of the desktop-computer market rather than the supercomputer market. As desktop processors became powerful enough to support real-time gaming and audio/video processing during the 1990s, demand grew for this type of computing power, and microprocessor vendors turned to SIMD to meet the demand.[2] This resurgence also coincided with the rise of [DirectX](/source/DirectX) and OpenGL shader models, which heavily leveraged SIMD under the hood. The graphics APIs encouraged programmers to adopt data-parallel programming styles, indirectly accelerating SIMD adoption in desktop software. Hewlett-Packard introduced [Multimedia Acceleration eXtensions](/source/Multimedia_Acceleration_eXtensions) (MAX) instructions into [PA-RISC](/source/PA-RISC) 1.1 desktops in 1994 to accelerate MPEG decoding.[3] Sun Microsystems introduced SIMD integer instructions in its "[VIS](/source/Visual_Instruction_Set)" instruction set extensions in 1995, in its [UltraSPARC I](/source/UltraSPARC) microprocessor. MIPS followed suit with their similar [MDMX](/source/MDMX) system.

The first widely deployed desktop SIMD was with Intel's [MMX](/source/MMX_(instruction_set)) extensions to the [x86](/source/X86) architecture in 1996. This sparked the introduction of the much more powerful [AltiVec](/source/AltiVec) system in the [Motorola](/source/Motorola) [PowerPC](/source/PowerPC) and IBM's [POWER](/source/IBM_Power_microprocessors) systems. Intel responded in 1999 by introducing the all-new [SSE](/source/Streaming_SIMD_Extensions) system. Since then, there have been several extensions to the SIMD instruction sets for both architectures. Advanced vector extensions AVX, [AVX2](/source/AVX2) and [AVX-512](/source/AVX-512) are developed by Intel. AMD supports AVX, [AVX2](/source/AVX2), and [AVX-512](/source/AVX-512) in their current products.[4]

## Disadvantages

With SIMD, an order of magnitude increase in code size is not uncommon, when compared to equivalent scalar or equivalent vector code, and an order of magnitude *or greater* effectiveness (work done per instruction) is achievable with Vector ISAs.[5]

ARM's [Scalable Vector Extension](/source/Scalable_Vector_Extension) takes another approach, known in [Flynn's Taxonomy](/source/Flynn's_taxonomy#Single_instruction_stream,_multiple_data_streams_(SIMD)) more commonly known today as ["Predicated" (masked)](/source/Predication_(computer_architecture)#SIMD,_SIMT_and_vector_predication) SIMD. This approach is not as compact as [vector processing](/source/Vector_processing) but is still far better than non-predicated SIMD. Detailed comparative examples are given at [Vector processor § Vector instruction example](/source/Vector_processor#Vector_instruction_example).

## Chronology

SIMD supercomputer examples excluding vector processors Year Example 1974 ILLIAC IV - an Array Processor comprising scalar 64-bit PEs 1974 ICL Distributed Array Processor (DAP) 1976 Burroughs Scientific Processor 1981 Geometric-Arithmetic Parallel Processor from Martin Marietta (continued at Lockheed Martin, then at Teranex and Silicon Optix) 1983–1991 Massively Parallel Processor (MPP), from NASA/Goddard Space Flight Center 1985 Connection Machine, models 1 and 2 (CM-1 and CM-2), from Thinking Machines Corporation 1987–1996 MasPar MP-1 and MP-2 1991 Zephyr DC from Wavetracer 2001 Xplor from Pyxsys, Inc.

## Hardware

### CPUs

Small-scale (64 or 128 bits) SIMD became popular on general-purpose CPUs in the early 1990s and continued through 1997 and later with Motion Video Instructions (MVI) for [Alpha](/source/DEC_Alpha). SIMD instructions can be found, to one degree or another, on most CPUs, including [IBM](/source/IBM)'s [AltiVec](/source/AltiVec) and Signal Processing Engine (SPE) for [PowerPC](/source/PowerPC), [Hewlett-Packard](/source/Hewlett-Packard)'s (HP) [PA-RISC](/source/PA-RISC) [Multimedia Acceleration eXtensions](/source/Multimedia_Acceleration_eXtensions) (MAX), [Intel](/source/Intel)'s [MMX and iwMMXt](/source/MMX_(instruction_set)), [Streaming SIMD Extensions](/source/Streaming_SIMD_Extensions) (SSE), [SSE2](/source/SSE2), [SSE3](/source/SSE3) [SSSE3](/source/SSSE3) and [SSE4](/source/SSE4).x, [AMD](/source/Advanced_Micro_Devices)'s [3DNow!](/source/3DNow!), [ARC's](/source/ARC_(processor)) ARC Video subsystem, [SPARC](/source/SPARC)'s [VIS](/source/Visual_Instruction_Set) and VIS2, [Sun](/source/Sun_Microsystems)'s [MAJC](/source/MAJC), [ARM's](/source/ARM_Holdings) [Neon](/source/ARM_architecture#Advanced_SIMD_(Neon)) technology, [MIPS](/source/MIPS_architecture)' [MDMX](/source/MDMX) (MaDMaX) and [MIPS-3D](/source/MIPS-3D).

Intel's [AVX-512](/source/AVX-512) SIMD instructions process 512 bits of data at once.

### Coprocessors

The IBM, Sony, Toshiba co-developed [Cell processor's](/source/Cell_(processor)) [Synergistic Processing Element's](/source/Cell_(processor)#Synergistic_Processing_Element_(SPE)) (SPE's) instruction set is heavily SIMD based.

Some, but not all, GPUs are SIMD-based. AMD GPUs since the [TeraScale (microarchitecture)](/source/TeraScale_(microarchitecture)) are SIMD-based, a feature that has remained in the 2020s microartectures RDNA and CDNA,[6] with a layer of [single instruction, multiple threads](/source/Single_instruction,_multiple_threads) (SIMT) above.[7] On the other hand, Nvidia's CUDA architectures use scalar cores with SIMT.[8]

[Philips](/source/Philips), now [NXP](/source/NXP_Semiconductors), developed several SIMD processors named [Xetal](/source/Xetal). The Xetal has 320 16-bit processor elements especially designed for vision tasks.

Apple's M1 and M2 chips also incorporate SIMD units deeply integrated with their GPU and Neural Engine, using Apple-designed SIMD pipelines optimized for image filtering, convolution, and matrix multiplication. This unified memory architecture helps SIMD instructions operate on shared memory pools more efficiently. (The CPU part implements ordinary NEON).

## Software

SIMD instructions are widely used to process 3D graphics, although modern [graphics cards](/source/Video_card) with embedded SIMD have largely taken over this task from the CPU. Some systems also include permute functions that re-pack elements inside vectors, making them especially useful for data processing and compression. They are also used in cryptography.[9][10][11] The trend of general-purpose computing on GPUs ([GPGPU](/source/GPGPU)) may lead to wider use of SIMD in the future. Recent compilers such as [LLVM](/source/LLVM), [GNU Compiler Collection](/source/GNU_Compiler_Collection) (GCC), and Intel's ICC offer aggressive auto-vectoring options. Developers can often enable these with flags like -O3 or -ftree-vectorize, which guide the compiler to restructure loops for SIMD compatibility.

Adoption of SIMD systems in [personal computer](/source/Personal_computer) software was at first slow, due to a number of problems. One was that many of the early SIMD instruction sets tended to slow overall performance of the system due to the re-use of existing floating point registers. Other systems, like [MMX](/source/MMX_(instruction_set)) and [3DNow!](/source/3DNow!), offered support for data types that were not interesting to a wide audience and had expensive context switching instructions to switch between using the [FPU](/source/Floating-point_unit) and MMX [registers](/source/Processor_register). Compilers also often lacked support, requiring programmers to resort to [assembly language](/source/Assembly_language) coding.

SIMD on [x86](/source/X86) had a slow start. The introduction of [3DNow!](/source/3DNow!) by [AMD](/source/Advanced_Micro_Devices) and [SSE](/source/Streaming_SIMD_Extensions) by [Intel](/source/Intel) confused matters somewhat, but today the system seems to have settled down (after AMD adopted SSE) and newer compilers should result in more SIMD-enabled software. Intel and AMD now both provide optimized math [libraries](/source/Library_(computing)) that use SIMD instructions, and open source alternatives like [libSIMD](/source/LibSIMD), [SIMDx86](/source/SIMDx86) and [SLEEF](/source/SLEEF) have started to appear (see also [libm](/source/Libm)).[12]

[Apple Computer](/source/Apple_Inc.) had somewhat more success, even though they entered the SIMD market later than the rest. [AltiVec](/source/AltiVec) offered a rich system and can be programmed using increasingly sophisticated compilers from [Motorola](/source/Motorola), [IBM](/source/IBM) and [GNU](/source/GNU), therefore assembly language programming is rarely needed. Additionally, many of the systems that would benefit from SIMD were supplied by Apple itself, for example [iTunes](/source/ITunes) and [QuickTime](/source/QuickTime). However, in 2006, Apple computers moved to Intel x86 processors. Apple's [APIs](/source/Application_programming_interface) and [development tools](/source/Integrated_development_environment) ([XCode](/source/Xcode)) were modified to support [SSE2](/source/SSE2) and [SSE3](/source/SSE3) as well as AltiVec. Apple was the dominant purchaser of PowerPC chips from IBM and [Freescale Semiconductor](/source/Freescale_Semiconductor). Even though Apple has stopped using PowerPC processors in their products, further development of AltiVec is continued in several PowerPC and [Power ISA](/source/Power_ISA) designs from Freescale and IBM.

*SIMD within a register*, or [SWAR](/source/SWAR), is a range of techniques and tricks used for performing SIMD in general-purpose registers on hardware that does not provide any direct support for SIMD instructions. This can be used to exploit parallelism in certain algorithms even on hardware that does not support SIMD directly.

### Programmer interface

It is common for publishers of the SIMD instruction sets to make their own [C](/source/C_(programming_language)) and [C++](/source/C%2B%2B) language extensions with [intrinsic functions](/source/Intrinsic_function) or special datatypes (with [operator overloading](/source/Operator_overloading)) guaranteeing the generation of vector code. Intel, AltiVec, and ARM NEON provide extensions widely adopted by the compilers targeting their CPUs. (More complex operations are the task of vector math libraries.)

#### Generic datatypes

The [GNU C Compiler](/source/GNU_C_Compiler) takes the extensions a step further by abstracting them into a universal interface that can be used on any platform by providing a way of defining SIMD datatypes.[13] The [LLVM](/source/LLVM) Clang compiler also implements the feature, with an analogous interface defined in the IR.[14] Rust's packed_simd crate (and the experimental std::simd) uses this interface, and so does [Swift](/source/Swift_(programming_language)) 2.0+.

C++ has an experimental interface std::experimental::simd that works similarly to the GCC extension. LLVM's libcxx seems to implement it.[citation needed] For GCC and libstdc++, a wrapper library that builds on top of the GCC extension is available.[15]

[Microsoft](/source/Microsoft_Corporation) added SIMD to [.NET](/source/.NET_Core) in RyuJIT.[16] The System.Numerics.Vector package, available on NuGet, implements SIMD datatypes.[17] Java also has a new proposed API for SIMD instructions available in [OpenJDK](/source/OpenJDK) 17 in an incubator module.[18] It also has a safe fallback mechanism on unsupported CPUs to simple loops.

#### Vectorization hints

Instead of providing an SIMD datatype, compilers can also be hinted to [auto-vectorize](/source/Automatic_vectorization) some loops, potentially taking some assertions about the lack of data dependency. This is not as flexible as manipulating SIMD variables directly, but is easier to use. [OpenMP](/source/OpenMP) 4.0+ has a #pragma omp simd hint.[19] This OpenMP interface has replaced a wide set of nonstandard extensions, including [Cilk](/source/Cilk)'s #pragma simd,[20] GCC's #pragma GCC ivdep, and many more.[21]

"SIMD everywhere", a collection of C/C++ headers implementing platform-specific intrinsics for other platforms (e.g. SSE intrinsics for ARM NEON), includes the use of platform-specific intrinsics, generic vector interfaces, and vectorization hints. It can be used as a "Rosetta Stone" for comparing these different SIMD programming paradigms.[22]

#### SPMD-on-SIMD

Another approach is [SPMD](/source/Single_program,_multiple_data): write a program that looks as if it operates only one element on the time, then have a compiler widen it to match the SIMD vector width. This is the approach used by graphics [shaders](/source/Shader) and more recently adopted by CPU-oriented tools such as Intel IPSC.[23]

### SIMD multi-versioning

Consumer software is typically expected to work on a range of CPUs covering multiple generations, which could limit the programmer's ability to use new SIMD instructions to improve the computational performance of a program. The solution is to include multiple versions of the same code that uses either older or newer SIMD technologies, and pick one that best fits the user's CPU at run-time ([dynamic dispatch](/source/Dynamic_dispatch)). There are two main camps of solutions:

- Function multi-versioning (FMV): a [subroutine](/source/Subroutine) in the program or a library is duplicated and compiled for many instruction set extensions, and the program decides which one to use at run-time.
- Library multi-versioning (LMV): the entire [programming library](/source/Library_(computing)) is duplicated for many instruction set extensions, and the operating system or the program decides which one to load at run-time.

FMV, manually coded in assembly language, is quite commonly used in a number of performance-critical libraries such as glibc and libjpeg-turbo. [Intel C++ Compiler](/source/Intel_C%2B%2B_Compiler), [GNU Compiler Collection](/source/GNU_Compiler_Collection) since GCC 6, and [Clang](/source/Clang) since clang 7 allow for a simplified approach, with the compiler taking care of function duplication and selection. GCC and clang requires explicit target_clones labels in the code to "clone" functions,[24] while ICC does so automatically (under the command-line option /Qax). The [Rust programming language](/source/Rust_programming_language) also supports FMV. The setup is similar to GCC and Clang in that the code defines what instruction sets to compile for, but cloning is manually done via inlining.[25]

As using FMV requires code modification on GCC and Clang, vendors more commonly use library multi-versioning: this is easier to achieve as only compiler switches need to be changed. [Glibc](/source/Glibc) supports LMV and this functionality is adopted by the Intel-backed Clear Linux project.[26]

### SIMD on the web

In 2013 John McCutchan announced that he had created a high-performance interface to SIMD instruction sets for the [Dart](/source/Dart_(programming_language)) programming language, bringing the benefits of SIMD to web programs for the first time. The interface consists of two types:[27]

- Float32x4, 4 single precision floating point values.
- Int32x4, 4 32-bit integer values.

Instances of these types are immutable and in optimized code are mapped directly to SIMD registers. Operations expressed in Dart typically are compiled into a single instruction without any overhead. This is similar to C and C++ intrinsics. Benchmarks for [4×4](/source/4%C3%974_matrix) [matrix multiplication](/source/Matrix_multiplication), [3D vertex transformation](/source/3D_vertex_transformation), and [Mandelbrot set](/source/Mandelbrot_set) visualization show near 400% speedup compared to scalar code written in Dart.

Intel announced at IDF 2013 that they were implementing McCutchan's specification for both [V8](/source/V8_(JavaScript_engine)) and [SpiderMonkey](/source/SpiderMonkey).[28] However, by 2017, SIMD.js was taken out of the [ECMAScript](/source/ECMAScript) standard queue in favor of pursuing a similar interface in [WebAssembly](/source/WebAssembly).[29]

Support for SIMD was added to the [WebAssembly](/source/WebAssembly) 2.0 specification, which was finished on 2022 and became official in December 2024.[30] LLVM's autovectoring, when compiling C or C++ to WebAssembly, can target WebAssembly SIMD to automatically make use of SIMD, while SIMD intrinsic are also available.[31]

## Commercial applications

It has generally proven difficult to find sustainable commercial applications for SIMD-only processors in general-purpose computing.

One that has had some measure of success is the [GAPP](/source/Geometric-Arithmetic_Parallel_Processor), which was developed by [Lockheed Martin](/source/Lockheed_Martin) and taken to the commercial sector by their spin-off [Teranex](/source/Teranex). The GAPP's recent incarnations have become a powerful tool in real-time [video processing](/source/Digital_image_processing) applications like conversion between various video standards and frame rates ([NTSC](/source/NTSC) to/from [PAL](/source/PAL), NTSC to/from [high-definition television](/source/High-definition_television) (HDTV) formats, etc.), [deinterlacing](/source/Deinterlacing), image [noise reduction](/source/Noise_reduction), adaptive [video compression](/source/Video_compression), and image enhancement.

A more ubiquitous application for SIMD is found in [video games](/source/Video_game): nearly every modern [video game console](/source/Video_game_console) since [1998](/source/History_of_video_game_consoles_(sixth_generation)) has incorporated a SIMD processor somewhere in its architecture. The [PlayStation 2](/source/PlayStation_2) was unusual in that one of its vector-float units could function as an autonomous [digital signal processor](/source/Digital_signal_processor) (DSP) executing its own instruction stream, or as a coprocessor driven by ordinary CPU instructions. 3D graphics applications tend to lend themselves well to SIMD processing as they rely heavily on operations with 4-dimensional vectors. [Microsoft](/source/Microsoft)'s [Direct3D](/source/Direct3D) 9.0 now chooses at runtime processor-specific implementations of its own math operations, including the use of SIMD-capable instructions.

A later processor that used vector processing is the [Cell processor](/source/Cell_(processor)) used in the PlayStation 3, which was developed by [IBM](/source/IBM) in cooperation with [Toshiba](/source/Toshiba) and [Sony](/source/Sony). It uses a number of SIMD processors (a [non-uniform memory access](/source/Non-uniform_memory_access) (NUMA) architecture, each with independent [local store](/source/Cache_memory) and controlled by a general purpose CPU) and is geared towards the huge datasets required by 3D and video processing applications. It differs from traditional ISAs by being SIMD from the ground up with no separate scalar registers.

Ziilabs produced an SIMD type processor for use on mobile devices, such as media players and mobile phones.[32]

Larger scale commercial SIMD processors are available from ClearSpeed Technology, Ltd. and Stream Processors, Inc. [ClearSpeed](/source/ClearSpeed)'s CSX600 (2004) has 96 cores each with two double-precision floating point units while the CSX700 (2008) has 192. Stream Processors is headed by computer architect [Bill Dally](/source/Bill_Dally). Their Storm-1 processor (2007) contains 80 SIMD cores controlled by a [MIPS](/source/MIPS_architecture) CPU.

## See also

- [Streaming SIMD Extensions](/source/Streaming_SIMD_Extensions), [MMX](/source/MMX_(instruction_set)), [SSE2](/source/SSE2), [SSE3](/source/SSE3), [Advanced Vector Extensions](/source/Advanced_Vector_Extensions), [AVX-512](/source/AVX-512)
- [Instruction set architecture](/source/Instruction_set_architecture)
- [Flynn's taxonomy](/source/Flynn's_taxonomy)
- SIMD within a register ([SWAR](/source/SWAR))
- [Single program, multiple data](/source/Single_program,_multiple_data) (SPMD)
- [OpenCL](/source/OpenCL)

## References

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1. Conte, G.; Tommesani, S.; Zanichelli, F. (2000). *The long and winding road to high-performance image processing with MMX/SSE*. Proc. Fifth IEEE Int'l Workshop on Computer Architectures for Machine Perception. [doi:10.1109/CAMP.2000.875989](https://doi.org/10.1109/CAMP.2000.875989). [hdl:11381/2297671](https://hdl.handle.net/11381/2297671). [S2CID 13180531](https://api.semanticscholar.org/CorpusID:13180531)

1. Lee, R.B. (1995). "Realtime MPEG video via software decompression on a PA-RISC processor". *digest of papers Compcon '95. Technologies for the Information Superhighway*. pp. 186–192. [doi:10.1109/CMPCON.1995.512384](https://doi.org/10.1109/CMPCON.1995.512384). ISBN 0-8186-7029-0. [S2CID 2262046](https://api.semanticscholar.org/CorpusID:2262046)

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1. Patterson, David & Waterman, Andrew (18 September 2017). ["SIMD Instructions Considered Harmful"](https://www.sigarch.org/simd-instructions-considered-harmful/). *SIGARCH*

1. Lam, Chester. ["GCN, AMD's GPU Architecture Modernization"](https://chipsandcheese.com/p/gcn-amds-gpu-architecture-modernization). *chipsandcheese.com*

1. Lam, Chester. ["Hot Chips 34 – AMD's Instinct MI200 Architecture"](https://chipsandcheese.com/p/hot-chips-34-amds-instinct-mi200-architecture). *chipsandcheese.com* On both NVIDIA and AMD, matrix instructions break the SIMT abstraction model and work across a whole wavefront (or “warp” on NVIDIA).

1. ["Version 2.3 8/27/2009 OpenCL Programming Guide for the CUDA Architecture"](https://www.nvidia.com/content/cudazone/download/opencl/nvidia_opencl_programmingguide.pdf)

1. [RE: SSE2 speed](http://marc.info/?l=openssl-dev&m=108530261323715&w=2), showing how SSE2 is used to implement SHA hash algorithms

1. [Salsa20 speed; Salsa20 software](http://cr.yp.to/snuffle.html#speed), showing a stream cipher implemented using SSE2

1. [Subject: up to 1.4x RSA throughput using SSE2](http://markmail.org/message/tygo74tyjagwwnp4), showing RSA implemented using a non-SIMD SSE2 integer multiply instruction.

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1. ["VcDevel/std-simd"](https://github.com/VcDevel/std-simd). VcDevel. 6 August 2020.

1. ["RyuJIT: The next-generation JIT compiler for .NET"](https://devblogs.microsoft.com/dotnet/ryujit-the-next-generation-jit-compiler-for-net). 30 September 2013.

1. ["The JIT finally proposed. JIT and SIMD are getting married"](https://devblogs.microsoft.com/dotnet/the-jit-finally-proposed-jit-and-simd-are-getting-married). 7 April 2014.

1. ["JEP 338: Vector API"](https://openjdk.java.net/jeps/338)

1. ["SIMD Directives"](https://www.openmp.org/spec-html/5.0/openmpsu42.html). *www.openmp.org*

1. ["Tutorial pragma simd"](https://web.archive.org/web/20201204055745/https://www.cilkplus.org/tutorial-pragma-simd). *CilkPlus*. 18 July 2012. Archived from [the original](https://www.cilkplus.org/tutorial-pragma-simd) on 4 December 2020. Retrieved 9 August 2020.

1. Kruse, Michael. ["OMP5.1: Loop Transformations"](https://www.openmp.org/wp-content/uploads/OpenMP_SC20_Loop_Transformations.pdf)

1. ["simd-everywhere/simde: Implementations of SIMD instruction sets for systems which don't natively support them."](https://github.com/simd-everywhere/simde). *GitHub*. SIMD Everywhere. 6 November 2025.

1. Pharr, Matt & Mark, William R. (May 2012). [*ispc: A SPMD compiler for high-performance CPU programming*](https://ispc.github.io/papers/ispc_inpar_2012.pdf). 2012 Innovative Parallel Computing (InPar). pp. 1–13. [doi:10.1109/InPar.2012.6339601](https://doi.org/10.1109/InPar.2012.6339601)

1. ["Function multi-versioning in GCC 6"](https://lwn.net/Articles/691932/). *lwn.net*. 22 June 2016.

1. ["2045-target-feature"](https://rust-lang.github.io/rfcs/2045-target-feature.html). *The Rust RFC Book*

1. ["Transparent use of library packages optimized for Intel® architecture"](https://clearlinux.org/news-blogs/transparent-use-library-packages-optimized-intel-architecture). *Clear Linux* Project*. Retrieved 8 September 2019.

1. John McCutchan. ["Bringing SIMD to the web via Dart"](https://www.dartlang.org/slides/2013/02/Bringing-SIMD-to-the-Web-via-Dart.pdf). [Archived](https://web.archive.org/web/20131203011540/https://www.dartlang.org/slides/2013/02/Bringing-SIMD-to-the-Web-via-Dart.pdf) 2013-12-03 at the Wayback Machine.

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## External links

- [SIMD architectures (2000)](https://arstechnica.com/articles/paedia/cpu/simd.ars)
- [Cracking Open The Pentium 3 (1999)](https://www.gamedeveloper.com/programming/wyatt-s-world-cracking-open-the-pentium-iii)
- [Short Vector Extensions in Commercial Microprocessor](http://www.eecg.toronto.edu/~corinna/vector/svx/)
- [Article about Optimizing the Rendering Pipeline of Animated Models Using the Intel Streaming SIMD Extensions](http://software.intel.com/en-us/articles/optimizing-the-rendering-pipeline-of-animated-models-using-the-intel-streaming-simd-extensions)
- ["Yeppp!": cross-platform, open-source SIMD library from Georgia Tech](https://web.archive.org/web/20130921070044/http://www.yeppp.info/)
- [Introduction to Parallel Computing from LLNL Lawrence Livermore National Laboratory](https://computing.llnl.gov/tutorials/parallel_comp/) [Archived](https://web.archive.org/web/20130610122229/https://computing.llnl.gov/tutorials/parallel_comp/) 2013-06-10 at the Wayback Machine

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Adapted from the Wikipedia article [Single instruction, multiple data](https://en.wikipedia.org/wiki/Single_instruction%2C_multiple_data) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Single_instruction%2C_multiple_data?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.