# Single-core

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Microprocessor containing a single core

A **single-core processor** is a microprocessor with a single [CPU](/source/CPU) on its [die](/source/Die_(integrated_circuit)).[1] It performs the [fetch-decode-execute cycle](/source/Instruction_cycle) one at a time, as it only runs on one [thread](/source/Thread_(computing)). A computer using a single core CPU is generally slower than a multi-core system.

Single core processors used to be widespread in desktop computers, but as applications demanded more processing power, the slower speed of single core systems became a detriment to performance. Windows supported single-core processors up until the release of [Windows 11](/source/Windows_11), where a dual-core processor is required.[2]

Single core processors are still in use in some niche circumstances. Some older legacy systems like those running antiquated operating systems (e.g. [Windows 98](/source/Windows_98)) cannot gain any benefit from multi-core processors. Single core processors are also used in hobbyist computers like the [Raspberry Pi](/source/Raspberry_Pi) and [Single-board microcontrollers](/source/Single-board_microcontroller). The production of single-core desktop processors ended in 2013 with the [Celeron](/source/Celeron) G440, G460, G465 & G470.[3]

## Development

The first single core processor was the [Intel 4004](/source/Intel_4004), which was commercially released on November 15, 1971 by [Intel](/source/Intel).[4] Since then many improvements have been made to single core processors, going from the 740 kHz of the Intel 4004 to the 2 GHz Celeron G470.[5]

### Advantages

- Single core processors draw less power than larger, multi-core processors.

- Single core processors can be made a lot more cheaply than multi core systems, meaning they can be used in embedded systems.

### Disadvantages

- Single-core processors are generally outperformed by multi-core processors.

- Single-core processors are more likely to bottleneck with faster peripheral components, as these components have to wait for the CPU to finish its cycle.[6]

- Single-core processors lack parallelisation, meaning only one application can run at once. This reduces performance as other processes have to wait for processor time, leading to [process starvation](/source/Starvation_(computer_science)).[7]

## Increasing parallel trend

- Single-core – one processor on a die. Since about 2012, most [smartphone](/source/Smartphone) [CPUs](/source/CPUs) marketed are no longer single-core; [Microcontrollers](/source/Microcontroller) are still single-core, while there are exceptions.[8]

- [Multi-core processors](/source/Multi-core_processor) – a 'few' processors on a die, e.g. 2, 4, 8.

- [Manycore processors](/source/Manycore_processor) – a 'large number' of processors on a die, e.g. 10s, 100s, 1000s. Some specialist [ASICs](/source/ASIC)/[Accelerators](/source/Hardware_acceleration) and [GPUs](/source/GPU) fall into this category.

## References

1. **[^](#cite_ref-1)** ["Single-core definition"](https://web.archive.org/web/20181115213054/http://www.yourdictionary.com/single-core). *Your Dictionary*. LoveToKnow. Archived from [the original](https://www.yourdictionary.com/single-core) on 15 November 2018. Retrieved 17 March 2022.

1. **[^](#cite_ref-2)** ["Windows 11 Minimum Requirements"](https://www.microsoft.com/en-gb/windows/windows-11-specifications). *Find Windows 11 specs, features and computer requirements*. Microsoft. Retrieved 17 March 2022.

1. **[^](#cite_ref-3)** ["The last single core CPU..."](http://www.andyscomputer.net/2021/01/the-last-single-core-cpu.html) *Andy's Computers*. 6 January 2021. Retrieved 17 March 2022.

1. **[^](#cite_ref-4)** ["Intel's First Microprocessor"](https://www.intel.com/content/www/us/en/history/museum-story-of-intel-4004.html). *The Story of the Intel 4004*. Intel. Retrieved 17 March 2022.

1. **[^](#cite_ref-5)** ["Intel Celerton Processor G470 Datasheet"](https://duckduckgo.com/?t=ffab&q=Celeron+G470&atb=v1-1&ia=web). *Intel Celeron Processor G470*. Intel. Retrieved 17 March 2022.

1. **[^](#cite_ref-6)** ["How To Properly Balance Your Components"](https://www.intel.com/content/www/us/en/gaming/resources/what-is-bottlenecking-my-pc.html). *What is Bottlenecking?*. Intel. Retrieved 17 March 2022.

1. **[^](#cite_ref-7)** Johnson, Ogundairo; Dinyo, Omosehinmi. ["Comparative Analysis of Single-Core and Multi-Core Systems"](https://aircconline.com/ijcsit/V7N6/7615ijcsit10.pdf) (PDF). *aircconline*. International Journal of Computer Science & Information Technology. Retrieved 17 March 2022.

1. **[^](#cite_ref-8)** Yiu, Joseph; Johnson, Ian. ["Multi-core microcontroller design with Cortex-M processors and CoreSight SoC"](https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-1989-00-00-00-00-52-92/Multi_2D00_core-microcontroller-design-with-Cortex_2D00_M-processors-and-Cor.pdf) (PDF). *ARM Community*. arm.com. Retrieved 17 March 2022.

v t e Processor technologies Models Abstract machine Stored-program computer Finite-state machine with datapath Hierarchical Deterministic finite automaton Queue automaton Cellular automaton Quantum cellular automaton Turing machine Alternating Turing machine Universal Post–Turing Quantum Nondeterministic Turing machine Probabilistic Turing machine Hypercomputation Zeno machine Belt machine Stack machine Register machines Counter Pointer Random-access Random-access stored program Architecture Microarchitecture Von Neumann Harvard modified Dataflow Transport-triggered Cellular Endianness Memory access NUMA HUMA Load–store Register/memory Cache hierarchy Memory hierarchy Virtual memory Secondary storage Heterogeneous Fabric Multiprocessing Cognitive Neuromorphic Instruction set architectures Types Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes Instruction sets Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False sharing Out-of-order Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue Speculative Branch prediction Memory dependence prediction Parallelism Level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed Multithreading Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD Processor performance Transistor count Instructions per cycle (IPC) Cycles per instruction (CPI) Instructions per second (IPS) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic updates per second (SUPS) Performance per watt (PPW) Cache performance metrics Computer performance by orders of magnitude Types Central processing unit (CPU) Graphics processing unit (GPU) GPGPU Vector Barrel Stream Tile processor Coprocessor PAL ASIC FPGA FPOA CPLD Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP) By application Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor Systems on chip System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC) Hardware accelerators Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor Word size 1-bit 4-bit 8-bit 12-bit 15-bit 16-bit 24-bit 32-bit 48-bit 64-bit 128-bit 256-bit 512-bit bit slicing others variable Core count Single-core Multi-core Manycore Heterogeneous architecture Components Core Cache CPU cache Scratchpad memory Data cache Instruction cache replacement policies coherence Bus Clock rate Clock signal FIFO Functional units Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder Logic Combinational Sequential Glue Logic gate Quantum Array Registers Processor register Status register Stack register Register file Memory buffer Memory address register Program counter Control unit Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter Datapath Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter Circuitry Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch Power management PMU APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Performance per watt (PPW) Related History of general-purpose CPUs Microprocessor chronology Processor design Digital electronics Hardware security module Semiconductor device fabrication Tick–tock model Pin grid array Chip carrier

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Adapted from the Wikipedia article [Single-core](https://en.wikipedia.org/wiki/Single-core) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Single-core?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.