# Serial communication > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Serial_communication > Markdown URL: https://mediated.wiki/source/Serial_communication.md > Source: https://en.wikipedia.org/wiki/Serial_communication > Source revision: 1343329597 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) Type of data transfer This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. Find sources: "Serial communication" – news · newspapers · books · scholar · JSTOR (August 2019) (Learn how and when to remove this message) Serial and parallel data transmission of 010010112. Standard bit sequence is least-significant-bit-first (D0 to D7 in ascending order).[1] D0 is received first via serial transmission. All bits are received simultaneously via parallel transmission. In [telecommunication](/source/Telecommunication) and [data transmission](/source/Data_transmission), **serial communication** is the process of sending [data](/source/Data) one [bit](/source/Bit) at a time, sequentially, over a [communication channel](/source/Communication_channel) or [computer bus](/source/Computer_bus). This is in contrast to [parallel communication](/source/Parallel_communication), where several bits are sent as a whole, on a link with several parallel channels. Standard character structure for asynchronous data communication consisting of 10 elements for a 7-bit ASCII character Serial communication is used for all [long-haul communication](/source/Long-haul_communications) and most [computer networks](/source/Computer_network), where the cost of [cable](/source/Electrical_cable) and difficulty of [synchronization](/source/Synchronization) make parallel communication impractical. Serial computer buses have become more common even at shorter distances, as improved [signal integrity](/source/Signal_integrity) and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or [SerDes](/source/SerDes)) and to outstrip its disadvantages ([clock skew](/source/Clock_skew), interconnect density). The migration from [PCI](/source/Peripheral_Component_Interconnect) to [PCI Express](/source/PCI_Express) (PCIe) is an example. Modern high speed serial interfaces such as PCIe[2][3][4] send data several bits at a time using modulation/encoding techniques such as [PAM4](/source/PAM4) which groups 2 bits at a time into a single symbol, and several symbols are still sent one at a time. This replaces PAM2 or non return to zero (NRZ) which only sends one bit at a time, or in other words one bit per symbol.[5][6][7][8][9][10][11][12] The symbols are sent at a speed known as the symbol rate or the baud rate.[13][14][15][16] ## Cables Many serial communication systems were originally designed to transfer data over relatively large distances through some sort of [data cable](/source/Data_cable). Practically all long-distance communication transmits data one bit at a time, rather than in parallel, because it reduces the cost of the cable. The cables that carry this data (other than "the" serial cable) and the [computer ports](/source/Computer_port_(hardware)) they plug into are usually referred to with a more specific name, to reduce confusion. Keyboard and mouse cables and ports are almost invariably serial—such as [PS/2 port](/source/PS%2F2_port), [Apple Desktop Bus](/source/Apple_Desktop_Bus) and [USB](/source/USB). The cables that carry digital video are also mostly serial—such as [coax cable](/source/Coax_cable) plugged into a [HD-SDI](/source/HD-SDI) port, a [webcam](/source/Webcam) plugged into a USB port or [FireWire port](/source/IEEE_1394), [Ethernet cable](/source/Ethernet_cable) connecting an [IP camera](/source/IP_camera) to a [Power over Ethernet](/source/Power_over_Ethernet) port, [FPD-Link](/source/FPD-Link), digital telephone lines (ex. [ISDN](/source/ISDN)), etc. Other such cables and ports, transmitting data one bit at a time, include [Serial ATA](/source/Serial_ATA), [Serial SCSI](/source/SCSI_connector#Serial_SCSI), Ethernet cable plugged into [Ethernet ports](/source/Ethernet_port), the [Display Data Channel](/source/Display_Data_Channel) using previously reserved pins of the [VGA connector](/source/VGA_connector) or the [DVI port](/source/DVI_port) or the [HDMI](/source/HDMI) port. ## Serial buses [RS-232](/source/RS-232) connector ([D-Sub](/source/D-Sub) DB-25 variant) Many communication systems were generally designed to connect two integrated circuits on the same [printed circuit board](/source/Printed_circuit_board), connected by [signal traces](/source/Signal_trace) on that board (rather than external cables). [Integrated circuits](/source/Integrated_circuit) are more expensive when they have more pins. To reduce the number of pins in a package, many ICs use a serial bus to transfer data when speed is not important. Some examples of such low-cost lower-speed serial buses include [RS-232](/source/RS-232), [DALI](/source/Digital_Addressable_Lighting_Interface), [SPI](/source/Serial_Peripheral_Interface_Bus), [CAN bus](/source/CAN_bus), [I²C](/source/I%C2%B2C), [UNI/O](/source/UNI%2FO), and [1-Wire](/source/1-Wire). Higher-speed serial buses include [USB](/source/USB), [SATA](/source/SATA) and [PCI Express](/source/PCI_Express). ## Serial versus parallel The communication links, across which computers (or parts of computers) talk to one another, may be either serial or parallel. A parallel link transmits several streams of data simultaneously along multiple channels (e.g., wires, printed circuit tracks, or optical fibers); whereas, a serial link transmits only a single stream of data. The rationale for parallel communication was the added benefit of having [Direct Memory Access](/source/Direct_Memory_Access) to the 8-bit or 16-bit registry addresses at a time when mapping direct data lanes was more convenient and faster than synchronizing data serially.[*[citation needed](https://en.wikipedia.org/wiki/Wikipedia:Citation_needed)*] Although a serial link may seem inferior to a parallel one, since it can transmit less data per clock cycle, it is often the case that serial links can be clocked considerably faster than parallel links in order to achieve a higher data rate. Several factors allow serial to be clocked at a higher rate: - [Clock skew](/source/Clock_skew) between different channels is not an issue (for unclocked [asynchronous serial communication](/source/Asynchronous_serial_communication) links). This can be caused by mismatched wire or conductor lengths.[17][18] - A serial connection requires fewer interconnecting cables (e.g., wires/fibers) and hence occupies less space. The extra space allows for better isolation of the channel from its surroundings. - [Crosstalk](/source/Crosstalk) is less of an issue, because there are fewer conductors in proximity.[17] - Budgets for power use, power dissipation, cable cost, component cost, IC die area, PC board area, ESD protection, etc. can be focused on a single link. The transition from parallel to serial buses was allowed by [Moore's law](/source/Moore's_law) which allowed for the incorporation of SerDes in integrated circuits.[19] An electrical serial link only requires a pair of wires, whereas a parallel link requires several. Thus serial links can save on costs (also known as the [Bill of Materials](/source/Bill_of_Materials)). [Differential signalling](/source/Differential_signalling) uses length-matched wires or conductors and are used in high speed serial links.[18] Length-matching is easier to perform on serial links as they require fewer conductors. In many cases, serial is cheaper to implement than parallel. Many [ICs](/source/Integrated_circuit) have serial interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore less expensive. ## Examples of architectures - [ARINC 818](/source/ARINC_818) Avionics Digital Video Bus - [Atari SIO](/source/Atari_SIO) (Joe Decuir credits his work on Atari SIO as the basis of USB) - [Binary Synchronous Communications](/source/Binary_Synchronous_Communications) BSC - Binary Synchronous Communications - [CAN](/source/CAN_bus) Control Area Network Vehicle Bus - [ccTalk](/source/CcTalk) Used in the money transaction and point-of-sale industry - [CoaXPress](/source/CoaXPress) industrial camera protocol over Coax - [DMX512](/source/DMX512) control of theatrical lighting - [Ethernet](/source/Ethernet) - [Fiber Distributed Data Interface](/source/Fiber_Distributed_Data_Interface) - [Fibre Channel](/source/Fibre_Channel) (high-speed, for connecting computers to mass storage devices) - [FireWire](/source/FireWire) - [HDMI](/source/HDMI) - [HyperTransport](/source/HyperTransport) - [InfiniBand](/source/InfiniBand) (very high speed, broadly comparable in scope to [PCI](/source/Peripheral_Component_Interconnect)) - [I²C](/source/I%C2%B2C) multidrop serial bus - [MIDI](/source/MIDI) control of electronic musical instruments - [MIL-STD-1553A/B](/source/MIL-STD-1553) - [Morse code](/source/Morse_code) [telegraphy](/source/Telegraphy) - [PCI Express](/source/PCI_Express) - [Profibus](/source/Profibus) - [RS-232](/source/RS-232) (low-speed, implemented by [serial ports](/source/Serial_port)) - [RS-422](/source/RS-422) multidrop serial bus - [RS-423](/source/RS-423) - [RS-485](/source/RS-485) multidrop multimaster serial bus - [SDI-12](/source/SDI-12) industrial sensor protocol - [SERCOM](/source/SERCOM) - [Serial ATA](/source/Serial_ATA) - [Serial Attached SCSI](/source/Serial_Attached_SCSI) - [Shift register](/source/Shift_register) with serial-in and serial-out configuration - [SONET](/source/SONET) and [SDH](/source/Synchronous_Optical_Networking) (high speed telecommunication over optical fibers) - [SpaceWire](/source/SpaceWire) Spacecraft communication network - [S/PDIF](/source/S%2FPDIF) and [AES3](/source/AES3) audio communication protocols - [SPI](/source/Serial_Peripheral_Interface_Bus) - [T-1](/source/T-carrier), [E-1](/source/E-carrier) and variants (high speed telecommunication over copper pairs) - [Universal Serial Bus](/source/Universal_Serial_Bus) (for connecting peripherals to computers) - [UNI/O](/source/UNI%2FO) multidrop serial bus - [1-Wire](/source/1-Wire) multidrop serial bus ## See also - [8N1](/source/8N1) - [Asynchronous serial communication](/source/Asynchronous_serial_communication) - [Comparison of synchronous and asynchronous signalling](/source/Comparison_of_synchronous_and_asynchronous_signalling) - [Computer bus](/source/Computer_bus) - [Data transmission](/source/Data_transmission) - [Eye pattern](/source/Eye_pattern) - [Federal Standard 1037C](/source/Federal_Standard_1037C) - [High-Level Data Link Control](/source/High-Level_Data_Link_Control) (HDLC) - [List of device bandwidths](/source/List_of_device_bandwidths) - [MIL-STD-188](/source/MIL-STD-188) - [Serial Peripheral Interface Bus](/source/Serial_Peripheral_Interface_Bus) - [Serial port](/source/Serial_port) - [Synchronous serial communication](/source/Synchronous_serial_communication) - [Universal asynchronous receiver/transmitter](/source/Universal_asynchronous_receiver%2Ftransmitter) (UART) ## References 1. **[^](#cite_ref-Mackenzie_1980_1-0)** Mackenzie, Charles E. (1980). [*Coded Character Sets, History and Development*](https://textfiles.meulie.net/bitsaved/Books/Mackenzie_CodedCharSets.pdf) (PDF). The Systems Programming Series (1 ed.). [Addison-Wesley Publishing Company, Inc.](/source/Addison-Wesley_Publishing_Company%2C_Inc.) pp. 247–253. [ISBN](/source/ISBN_(identifier)) [978-0-201-14460-4](https://en.wikipedia.org/wiki/Special:BookSources/978-0-201-14460-4). [LCCN](/source/LCCN_(identifier)) [77-90165](https://lccn.loc.gov/77-90165). [Archived](https://web.archive.org/web/20160526172151/https://textfiles.meulie.net/bitsaved/Books/Mackenzie_CodedCharSets.pdf) (PDF) from the original on May 26, 2016. Retrieved December 29, 2022. 1. **[^](#cite_ref-2)** Robinson, Dan (12 January 2022). ["Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023"](https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/). *[The Register](/source/The_Register)*. 1. **[^](#cite_ref-3)** ["PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025"](https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming). Archived from [the original](https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming) on April 4, 2024. 1. **[^](#cite_ref-4)** ["PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here"](https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/). 12 January 2022. 1. **[^](#cite_ref-5)** [*Handbook of Serial Communications Interfaces: A Comprehensive Compendium of Serial Digital Input/Output (I/O) Standards*](https://books.google.com/books?id=wnGDBAAAQBAJ&dq=serial+pam4+signals&pg=PA9). Newnes. 21 August 2015. [ISBN](/source/ISBN_(identifier)) [978-0-12-800671-9](https://en.wikipedia.org/wiki/Special:BookSources/978-0-12-800671-9). 1. **[^](#cite_ref-6)** ["PAM4: For Better and Worse | 2019-02-26 | Signal Integrity Journal"](https://www.signalintegrityjournal.com/articles/1151-pam4-for-better-and-worse). 1. **[^](#cite_ref-7)** ["PAM-4 Signaling"](https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/). 1. **[^](#cite_ref-8)** Zhang, Hongtao; Jiao, Brandon; Liao, Yu; Zhang, Geoff. [*PAM4 Signaling for 56G Serial Link Applications − A Tutorial*](https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf) (PDF). DesignCon 2016. 1. **[^](#cite_ref-9)** ["PAM4 Signaling in High-Speed Serial Technology: Test, Analysis, and Debug"](https://download.tek.com/document/PAM4-Signaling-in-High-Speed-Serial-Technology_55W-60273.pdf) (PDF) (application note). [Tektronix](/source/Tektronix). 1. **[^](#cite_ref-10)** Pan, Zhongqi; Yue, Yang (3 December 2019). [*Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications*](https://books.google.com/books?id=JljBDwAAQBAJ&dq=pam4+symbol&pg=PA54). [ISBN](/source/ISBN_(identifier)) [978-3-03921-792-2](https://en.wikipedia.org/wiki/Special:BookSources/978-3-03921-792-2). 1. **[^](#cite_ref-11)** [*Essentials of Modern Communications*](https://books.google.com/books?id=MlruDwAAQBAJ&dq=pam4+symbol&pg=PA944). John Wiley & Sons. 4 August 2020. [ISBN](/source/ISBN_(identifier)) [978-1-119-52149-5](https://en.wikipedia.org/wiki/Special:BookSources/978-1-119-52149-5). 1. **[^](#cite_ref-12)** Kim, Gain (January 2022). ["Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications"](https://www.researchgate.net/figure/Eye-diagrams-of-PAM-2-4-8-with-normalized-vertical-full-swing-level-Peak-to-peak-swings_fig2_361960252). *IEEE Open Journal of Circuits and Systems*. **3** (1). Figure 2. [doi](/source/Doi_(identifier)):[10.1109/OJCAS.2022.3189550](https://doi.org/10.1109%2FOJCAS.2022.3189550). [ISSN](/source/ISSN_(identifier)) [2644-1225](https://search.worldcat.org/issn/2644-1225). 1. **[^](#cite_ref-13)** ["Eye diagrams: The tool for serial data analysis"](https://www.edn.com/eye-diagrams-the-tool-for-serial-data-analysis/). 4 June 2019. 1. **[^](#cite_ref-14)** ["Advantages of PAM4 modulation | Disadvantages PAM4 signaling"](https://www.rfwireless-world.com/Terminology/Advantages-and-disadvantages-of-PAM4-modulation.html). 1. **[^](#cite_ref-15)** ["Generate PAM4 signals for receiver compliance testing"](https://www.edn.com/generate-pam4-signals-for-receiver-compliance-testing/). 20 September 2016. 1. **[^](#cite_ref-16)** [*Complex Digital Hardware Design*](https://books.google.com/books?id=L1YIEQAAQBAJ&dq=pam4+symbol+rate&pg=PA16). CRC Press. 9 May 2024. [ISBN](/source/ISBN_(identifier)) [978-1-040-01179-9](https://en.wikipedia.org/wiki/Special:BookSources/978-1-040-01179-9). 1. ^ [***a***](#cite_ref-cse378-lecture-24_17-0) [***b***](#cite_ref-cse378-lecture-24_17-1) ["Lecture 24"](https://courses.cs.washington.edu/courses/cse378/11wi/lectures/lec24.pdf) (PDF). *CSE378: Machine Organization & Assembly Language*. 1. ^ [***a***](#cite_ref-Packt_Publishing_18-0) [***b***](#cite_ref-Packt_Publishing_18-1) Ledin, Jim; Farley, Dave (4 May 2022). [*Modern Computer Architecture and Organization: Learn x86, ARM, and RISC-V architectures and the design of smartphones, PCs, and cloud servers*](https://books.google.com/books?id=BxptEAAAQBAJ). Packt Publishing. [ISBN](/source/ISBN_(identifier)) [978-1-80323-823-4](https://en.wikipedia.org/wiki/Special:BookSources/978-1-80323-823-4). 1. **[^](#cite_ref-19)** [*The Boundary — Scan Handbook*](https://books.google.com/books?id=aUCgNOpyUbgC&dq=parallel++serial++serdes+moore%27s+law&pg=PA275). Springer. 30 June 2003. [ISBN](/source/ISBN_(identifier)) [978-1-4020-7496-7](https://en.wikipedia.org/wiki/Special:BookSources/978-1-4020-7496-7). ## External links - [Serial Interface Tutorial for Robotics](http://www.societyofrobots.com/microcontroller_uart.shtml) (contains many practical examples) - [Serial interfaces listing (with pinouts)](https://pinouts.ru/pin_SerialPorts.shtml) - [Wiki: Serial Ports](http://c2.com/cgi/wiki?SerialPorts) - [Visual studio 2008 coding for Serial communication](https://web.archive.org/web/20090226195855/http://www.thaiio.com/prog-cgi/VBnetSerialPort.htm) - [Introduction to I²C and SPI protocols](http://www.byteparadigm.com/kb/article/AA-00255) [Archived](https://web.archive.org/web/20160308185505/http://byteparadigm.com/kb/article/aa-00255) 2016-03-08 at the [Wayback Machine](/source/Wayback_Machine) - [Serial communication introduction](https://learn.sparkfun.com/tutorials/serial-communication/all) - [Serial Port Programming in Linux](https://training-kits.appspot.com/serial-linux.html) [Archived](https://web.archive.org/web/20180702014758/http://training-kits.appspot.com/serial-linux.html) 2018-07-02 at the [Wayback Machine](/source/Wayback_Machine) v t e Technical and de facto standards for wired computer buses General System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play Double data rate Quad data rate List of bus bandwidths Standards SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire Storage ST-506 ESDI SDI IPI SMD Floppy connector Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface) Peripheral Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt CAN bus Audio ADAT Lightpipe AES3 Intel HD Audio I2S MADI McASP S/PDIF TOSLINK Portable PC Card ExpressCard Embedded Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category v t e Line coding (digital baseband transmission) Main articles Unipolar encoding Bipolar encoding On–off keying Mark and space Basic line codes Return to zero (RZ) Non-return-to-zero, level (NRZ/NRZ-L) Non-return-to-zero, inverted (NRZ-I) Non-return-to-zero, space (NRZ-S) Manchester Differential Manchester/biphase (Bi-φ) Extended line codes Conditioned diphase 4B3T 4B5B 2B1Q Alternate mark inversion Modified AMI code Coded mark inversion MLT-3 encoding Hybrid ternary code 6b/8b encoding 8b/10b encoding 64b/66b encoding Eight-to-fourteen modulation Delay/Miller encoding TC-PAM Optical line codes Carrier-Suppressed Return-to-Zero Alternate-Phase Return-to-Zero See also: Baseband Baud Bit rate Digital signal Digital transmission Ethernet physical layer Pulse modulation methods Pulse-amplitude modulation (PAM) Pulse-code modulation (PCM) Serial communication Category:Line codes --- Adapted from the Wikipedia article [Serial communication](https://en.wikipedia.org/wiki/Serial_communication) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Serial_communication?action=history)). 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