# Serial Peripheral Interface

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Synchronous serial communication interface

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Serial Peripheral Interface (SPI) Type Serial communication bus Production history Designer Motorola Designed Around early 1980s[note 1] Manufacturer Various Daisy chain Depends on devices Connector Unspecified Electrical Max. voltage Unspecified Max. current Unspecified Data Width 1 bit (bidirectional) Max. devices Multidrop limited by slave selects. Daisy chaining unlimited. Protocol Full-duplex serial Pinout MOSI Master Out Slave In MISO Master In Slave Out SCLK Serial Clock SS Slave Select (one or more) (pins may have alternative names)

**Serial Peripheral Interface** (**SPI**) is a [de facto standard](/source/De_facto_standard) (with many [variants](#Variations)) for [synchronous](/source/Comparison_of_synchronous_and_asynchronous_signalling) [serial communication](/source/Serial_communication), used primarily in [embedded systems](/source/Embedded_systems) for short-distance [wired communication](/source/Wired_communication) between [integrated circuits](/source/Integrated_circuits).

SPI follows a [master–slave architecture](/source/Master%E2%80%93slave_(technology)),[1] where a device (variously called master, leader, controller, main...) [orchestrates communication](/source/Signaling_(telecommunications)) with one or more devices (variously called slave, follower, target, sub...) by driving the [clock](/source/Clock_signal) and [chip select](/source/Chip_select) signals. As there is no formal standard, some manufacturers introduce devices with the ability to change their roles on the fly.

[Motorola](/source/Motorola)'s original specification (from the early 1980s) uses four [logic signals](/source/Logic_signal), aka lines or wires, to support [full duplex](/source/Full_duplex) communication. It is sometimes called a *four-wire* [serial bus](/source/Serial_bus) to contrast with [three-wire](#Three-wire) variants which are [half duplex](/source/Half_duplex), and with the *two-wire* [I²C](/source/I%C2%B2C) and [1-Wire](/source/1-Wire) serial buses.

Typical [applications](#Applications) include interfacing [microcontrollers](/source/Microcontrollers) with peripheral chips for [Secure Digital](/source/Secure_Digital) cards, [liquid crystal displays](/source/Liquid_crystal_display), [analog-to-digital](/source/Analog-to-digital) and [digital-to-analog converters](/source/Digital-to-analog_converters), [flash](/source/Flash_memory#Serial_flash) and [EEPROM](/source/EEPROM#Serial_bus_devices) memory, and various communication chips.

Although SPI is a synchronous serial interface,[2] it is different from [Synchronous Serial Interface](/source/Synchronous_Serial_Interface) (SSI). SSI employs [differential signaling](/source/Differential_signaling) and provides only a single [simplex communication](/source/Simplex_communication) channel.

## Operation

Single master to single slave: basic SPI wiring

Commonly, SPI has four logic signals. [Variations](#Variations) may use different [names](#Alternative_terminology) or have different signals.

- Abbr. Name Description SS Slave Select Active-low chip select signal from master to enable communication with a specific slave device SCLK Serial Clock Clock signal from master MOSI Master Out Slave In Serial data output from master MISO Master In Slave Out Serial data output from slave

MOSI on a master outputs to MOSI on a slave. MISO on a slave outputs to MISO on a master.

Each device internally uses a [shift register](/source/Shift_register) for serial communication, which together forms an inter-chip [circular buffer](/source/Circular_buffer).

To support multidrop bus, slave devices should use [tri-state outputs](/source/Tri-state_output) so their MISO signal becomes [high impedance](/source/High_impedance) (electrically disconnected) when the device is not selected. Slaves without tri-state outputs cannot share a MISO line with other slaves without using an external tri-state buffer.

### Data transmission

A typical hardware setup using two [shift registers](/source/Shift_register) to form an inter-chip [circular buffer](/source/Circular_buffer)

Serial Peripheral Interface animation. This animation shows a scenario where the master sends 8-bit data and simultaneously reads 16-bit data from the slave. The lower boxes represent the device's memories.

To begin communication, the SPI master first selects the device it wants to communicate with by pulling its SS low. (The bar above SS indicates it is an [active low](/source/Active_low) signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.[note 2]

During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits). The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters.

Data is usually shifted out with the [most-significant bit](/source/Most-significant_bit) (MSB) first but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

If a single slave device is used, its SS pin *may* be fixed to [logic low](/source/Logic_level) if the slave permits it. With multiple slave devices, a [multidrop configuration](#Multidrop_configuration) requires an independent SS signal from the master for each slave device, while a [daisy-chain configuration](#Daisy_chain_configuration) only requires one SS signal.

Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [contention](/source/Bus_contention) on MISO, non-selected slaves must use [tristate](/source/Three-state_logic) output. Slaves that are not already tristate will need external tristate buffers to ensure this.[3]

### Clock polarity and phase

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola[4][5] named these two options as CPOL and CPHA (for **c**lock **pol**arity and **c**lock **pha**se) respectively, a convention most vendors have also adopted.

SPI [timing diagram](/source/Digital_timing_diagram) for both clock polarities and phases. Data bits output on blue lines if CPHA=0, or on red lines if CPHA=1, and sample on opposite-colored lines. Numbers identify data bits. Z indicates [high impedance](/source/High_impedance).

The SPI [timing diagram](/source/Digital_timing_diagram) shown is further described below:

- CPOL represents the polarity of the clock. Polarities can be converted with a simple [inverter](/source/Inverter_(logic_gate)). - SCLKCPOL=0 is a clock which idles at the [logical low](/source/Logical_low) voltage. - SCLKCPOL=1 is a clock which idles at the logical high voltage.

- CPHA represents the [phase](/source/Phase_(waves)) of each data bit's transmission cycle relative to SCLK. - For CPHA=0: - The first data bit is output *immediately* when SS activates. - Subsequent bits are output when SCLK transitions *to* its idle voltage level. - Sampling occurs when SCLK transitions *from* its idle voltage level. - For CPHA=1: - The first data bit is output on SCLK's first clock edge *after* SS activates. - Subsequent bits are output when SCLK transitions *from* its idle voltage level. - Sampling occurs when SCLK transitions *to* its idle voltage level. - Conversion between these two phases is non-trivial. - MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

### Mode numbers

The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:

SPI mode Clock polarity (CPOL) Clock phase (CPHA) Data is shifted out on Data is sampled on 0 0 0 falling SCLK, and when SS activates rising SCLK 1 0 1 rising SCLK falling SCLK 2 1 0 rising SCLK, and when SS activates falling SCLK 3 1 1 falling SCLK rising SCLK

Notes:

- Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.

- In Full Duplex operation, the master device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.

- Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.

### Valid communications

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's [scan chain](/source/Scan_chain) by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

### Interrupts

Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may be implemented optionally.

#### From master to slave

Microcontrollers configured as slave devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive [FIFO](/source/FIFO_(electronic)) buffer,[6] and may also set up an interrupt routine when their slave select input line is pulled low or high.

#### From slave to master

SPI slaves sometimes use an [out-of-band signal](/source/Out-of-band_signal) (another wire) to send an interrupt signal to a master. Examples include pen-down interrupts from [touchscreen](/source/Touchscreen) sensors, thermal limit alerts from [temperature sensors](/source/List_of_temperature_sensors), alarms issued by [real-time clock](/source/Real-time_clock) chips, [SDIO](/source/Secure_Digital#SDIO)[note 3] and [audio jack](/source/Audio_jack) insertions for an [audio codec](/source/Audio_codec). Interrupts to master may also be faked by using [polling](/source/Polling_(computer_science)) (similarly to [USB 1.1](/source/USB_1.1) and [2.0](/source/USB_2.0)).

## Bus topologies

Though the previous operation section focused on a basic interface with a single slave, SPI can instead communicate with multiple slaves using multidrop, daisy chain, or expander configurations.

### Multidrop configuration

Multidrop SPI bus

In the [multidrop bus](/source/Multidrop_bus) configuration, each slave has its own SS, and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its SS signal.[3] (Since only a single signal line needs to be tristated per slave, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an SPI bus)

Caveat: All SS signals should start high (to indicate no slaves are selected) before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses [general-purpose input/output (GPIO) pins](/source/General-purpose_input%2Foutput) (which may default to an undefined state) for SS and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for SS to output a high voltage for *all* slaves *before* running initialization code from any of those software libraries. Another solution is to add a [pull-up resistor](/source/Pull-up_resistor) on each SS, to ensure that all SS signals are initially high.[3]

### Daisy chain configuration

Daisy-chained SPI

Some products that implement SPI may be connected in a [daisy chain](/source/Daisy_chain_(electrical_engineering)) configuration, where the first slave's output is connected to the second slave's input, and so on with subsequent slaves, until the final slave, whose output is connected back to the master's input. This effectively merges the individual communication shift registers of each slave to form a single larger combined [shift register](/source/Shift_register) that shifts data through the chain. This configuration only requires a single SS line from the master, rather than a separate SS line for each slave.[7]

In addition to using SPI-specific slaves, daisy-chained SPI can include [discrete](/source/Discrete_component) shift registers for [more pins](/source/Shift_register#More_I/O_pins) of inputs (e.g. using the [parallel-in serial-out](/source/Shift_register#Parallel-in_serial-out_(PISO)) [74](/source/List_of_7400-series_integrated_circuits)xx165)[8] or outputs (e.g. using the [serial-in parallel-out](/source/Shift_register#Serial-in_parallel-out_(SIPO)) [74](/source/List_of_7400-series_integrated_circuits)xx595)[9] chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include [SGPIO](/source/SGPIO), [JTAG](/source/JTAG),[10] and [I2C](/source/I2C).

### Expander configurations

Expander configurations use SPI-controlled addressing units (e.g. [binary decoders](/source/Binary_decoder), [demultiplexers](/source/Demultiplexer), or shift registers) to add chip selects.

For example, one SS can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another SS is routed through that demultiplexer according to that index to select the desired slave.[11]

## Pros and cons

### Advantages

- Full duplex communication in the default version of this protocol

- [Push–pull drivers](/source/Push%E2%80%93pull_output) (as opposed to [open drain](/source/Open_drain)) provide relatively good signal integrity and high speed

- Higher [throughput](/source/Throughput) than [I²C](/source/I%C2%B2C) or [SMBus](/source/System_Management_Bus) - SPI's protocol has no maximum clock speed, however: - Individual devices specify acceptable clock frequencies - Wiring and electronics limit frequency

- Complete protocol flexibility for the bits transferred - Not limited to 8-bit symbols - Arbitrary choice of message size, content, and purpose

- Simple hardware and interfacing - Hardware implementation for slaves only requires a selectable shift register - Slaves use the master's clock and hence do not need precision oscillators - Slaves do not need a unique [address](/source/Address_space) – unlike [I²C](/source/I%C2%B2C) or [GPIB](/source/GPIB) or [SCSI](/source/SCSI) - Masters only additionally require generation of clock and SS signals - Results in simple bit-banged software implementation - Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than [parallel interfaces](/source/Parallel_communication) - At most one unique signal per device (SS); all others are shared - The daisy-chain configuration does not need more than one shared SS - Typically lower power requirements than [I²C](/source/I%C2%B2C) or SMBus due to less circuitry (including pull up resistors) - Single master means no [bus arbitration](/source/Bus_arbitration) (and associated failure modes) - unlike [CAN-bus](/source/CAN-bus) - Transceivers are not needed - unlike [CAN-bus](/source/CAN-bus) - Signals are unidirectional, allowing for easy [galvanic isolation](/source/Galvanic_isolation)

### Disadvantages

- Requires more pins on IC packages than [I²C](/source/I%C2%B2C), even in [three-wire](#Three-wire) variants

- Only handles short distances compared to [RS-232](/source/RS-232), [RS-485](/source/RS-485), or [CAN-bus](/source/CAN-bus) (though distance can be extended with the use of transceivers like [RS-422](/source/RS-422))

- Extensibility severely reduced when multiple slaves using different SPI Modes are required - Access is slowed down when master frequently needs to reinitialize in different modes

- No formal standard - So validating conformance is not possible - Many existing variations complicate support

- No built-in protocol support for some conveniences: - No hardware [flow control](/source/Flow_control_(data)) by the slave (but the master can delay the next clock edge to slow the transfer rate) - No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it) - No error-checking protocol - No [hot swapping](/source/Hot_swapping) (dynamically adding nodes) - Interrupts are outside the scope of SPI (see [§ Interrupts](#Interrupts))

## Applications

SPI Memory by [Atmel](/source/Atmel)

[Fairchild](/source/Fairchild_Semiconductor) EEPROM using [Microwire](#Microwire)

[Microchip](/source/Microchip_Technology) 32-Mbit [SQI](#QPI/SQI) Flash Memory

SPI is used to talk to a variety of peripherals, such as

- Sensors: [temperature](/source/Temperature), [pressure](/source/Pressure), [ADC](/source/Analog-to-digital_converter), [touchscreens](/source/Touchscreens), [video game controllers](/source/Video_game_controllers)

- Control devices: [audio codecs](/source/Audio_codec), [digital potentiometers](/source/Digital_potentiometer), [DACs](/source/Digital-to-analog_converter)

- Camera lenses: [Canon EF lens mount](/source/Canon_EF_lens_mount)

- Memory: [flash](/source/Flash_memory#Serial_flash) and [EEPROMs](/source/EEPROM#Serial_bus_devices) - Any [MMC](/source/MultiMediaCard) or [SD](/source/Secure_Digital) card (including [SDIO](/source/Secure_Digital#SDIO) variant[note 3])

- [Real-time clocks](/source/Real-time_clock)

- [LCDs](/source/LCD), sometimes even for managing image data

- [Shift registers](/source/Shift_registers) for additional I/O[8][9]

[Board](/source/Printed_circuit_board) real estate and wiring savings compared to a [parallel](/source/Parallel_communication) bus are significant, and have earned SPI a solid role in embedded systems. That is true for most [system-on-a-chip](/source/System-on-a-chip) processors, both with higher-end 32-bit processors such as those using [ARM](/source/ARM_architecture), [MIPS](/source/MIPS_architecture), or [PowerPC](/source/PowerPC) and with lower-end microcontrollers such as the [AVR](/source/Atmel_AVR), [PIC](/source/PIC_microcontroller), and [MSP430](/source/MSP430). These chips usually include SPI controllers capable of running in either master or slave mode. [In-system programmable](/source/In-system_programming) AVR controllers (including blank ones) can be programmed using SPI.[12]

Chip or [FPGA](/source/FPGA) based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin. And for high-performance systems, [FPGAs](/source/FPGA) sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as [digital audio](/source/Digital_audio), [digital signal processing](/source/Digital_signal_processing), or [telecommunications channels](/source/Channel_(communications)), but most off-the-shelf chips stick to half-duplex request/response protocols.

## Variations

SPI implementations have a wide variety of protocol variations. Some devices are transmit-only; others are receive-only. Slave selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols.

### Original definition

[Motorola](/source/Motorola) in 1983 listed[13] three [6805](/source/Motorola_6805) 8-bit [microcomputers](/source/Microcomputer) that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual.[14]

#### AN991

Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"[15] (now under [NXP](/source/NXP_Semiconductors), last revised 2002[5]) informally serves as the "official" defining document for SPI.

### Timing variations

Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response.

Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the slave select line.

### Transmission size

Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the [JTAG](/source/JTAG) or [SGPIO](/source/SGPIO) protocols, or any other protocol that requires messages that are not multiples of 8 bits.

### No slave select

Some devices do not use slave select, and instead manage protocol state machine entry/exit using other methods.

### Connectors

Anyone needing an external connector for SPI defines their own or uses another standard connection such as: [UEXT](/source/UEXT), [Pmod](/source/Pmod_Interface), various [JTAG connectors](/source/JTAG_connector), [Secure Digital](/source/Secure_Digital) card socket, etc.

### Flow control

Some devices require an additional [flow control](/source/Flow_control_(data)) signal from slave to master, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a *ready* or *enable* signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

### SafeSPI

SafeSPI[16] is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

### High reliability modifications

In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of [common mode noise](/source/Common_mode_signal) by adapting SPI to use [low-voltage differential signaling](/source/Low-voltage_differential_signaling).[17] Another advantage is that the controlled devices can be designed to loop-back to test signal integrity.[18]

### Intelligent SPI controllers

A **Queued Serial Peripheral Interface** (**QSPI**; different to but has same abbreviation as *Quad SPI* described in [§ Quad SPI](#Quad_SPI)) is a type of SPI controller that uses a [data queue](/source/Queue_(data_structure)) to transfer data across an SPI bus.[19] It has a [wrap-around](/source/Circular_buffer) mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as [memory-mapped](/source/Virtual_memory) parallel devices. This feature is useful in applications such as control of an [A/D converter](/source/Analog-to-digital_converter). Other programmable features in Queued SPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such [direct memory access](/source/Direct_memory_access) (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by **Multichannel Buffered Serial Port** (**MCBSP**).[note 4] Most SPI master controllers integrate support for up to four slave selects,[note 5] although some require slave selects to be managed separately through GPIO lines.

Note that *Queued SPI* is different from *Quad SPI*, and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode![20]

### Three-wire

Three-wire variants of SPI restricted to a [half-duplex](/source/Half-duplex) mode use a single bidirectional data line called SISO (slave out/slave in) or MOMI (master out/master in) instead of SPI's two unidirectional lines (MOSI and MISO). Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and [Microwire](#Microwire). Few SPI controllers support this mode, although it can be easily [bit-banged](/source/Bit-banging) in software.

### Bit-width extensions

#### Dual SPI

For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:[21][22]

- Dual read sends the command and address from the master in single mode, and returns the data in dual mode.

- Dual I/O sends the command in single mode, then sends the address and return data in dual mode.

#### Quad SPI

**Quad SPI** (**QSPI**; different to but has same abbreviation as *Queued-SPI* described in [§ Intelligent SPI controllers](#Intelligent_SPI_controllers)) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.[21][22]

**SQI Type 1**
- Commands sent on single line but addresses and data sent on four lines

**SQI Type 2**
- Commands and addresses sent on a single line but data sent/received on four lines

#### QPI/SQI

Further extending quad SPI, some devices support a "quad everything" mode where *all* communication takes place over 4 data lines, including commands.[23] This is variously called "QPI"[22] (not to be confused with [Intel QuickPath Interconnect](/source/Intel_QuickPath_Interconnect)) or "serial quad I/O" (SQI)[24]

This requires programming a configuration bit in the device and requires care after reset to establish communication.

### Double data rate

In addition to using multiple lines for I/O, some devices increase the transfer rate by using [double data rate](/source/Double_data_rate) transmission.[25][26]

### SGPIO

Main article: [SGPIO](/source/SGPIO)

[SGPIO](/source/SGPIO) is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.[*[citation needed](https://en.wikipedia.org/wiki/Wikipedia:Citation_needed)*] SGPIO uses 3-bit messages.

### Intel's Enhanced Serial Peripheral Interface

[Intel](/source/Intel) has developed a successor to its [Low Pin Count](/source/Low_Pin_Count) (LPC) bus that it calls the **Enhanced Serial Peripheral Interface** (**eSPI**) bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous [out-of-band](/source/Out-of-band_signal) pins through eSPI, and allow system designers to trade off cost and performance.[27][28]

An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.[27]

This standard defines an Alert# signal that is used by an eSPI slave to request service from the master. In a performance-oriented design or a design with only one eSPI slave, each eSPI slave will have its Alert# pin connected to an Alert# pin on the eSPI master that is dedicated to each slave, allowing the eSPI master to grant low-latency service, because the eSPI master will know which eSPI slave needs service and will not need to poll all of the slaves to determine which device needs service. In a budget design with more than one eSPI slave, all of the Alert# pins of the slaves are connected to one Alert# pin on the eSPI master in a [wired-OR](/source/Wired-OR) connection, which requires the master to poll all the slaves to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing service and therefore pulling the Alert# signal low.[27]

This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66 MHz to further allow designers to trade off performance and cost.[27]

Communications that were out-of-band of LPC like [general-purpose input/output](/source/General-purpose_input%2Foutput) (GPIO) and [System Management Bus](/source/System_Management_Bus) (SMBus) should be tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.[27]

This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one-half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.[27]

eSPI slaves are allowed to use the eSPI master as a proxy to perform flash operations on a standard SPI flash memory slave on behalf of the requesting eSPI slave.[27]

64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.[27]

The Intel [Z170 chipset](/source/Z170) can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24 MHz instead of the standard 33 MHz.[29]

The eSPI bus is also adopted by [AMD Ryzen](/source/AMD_Ryzen) chipsets.

## Interoperability with other standards

### Microwire

Microwire,[30] often spelled **μWire**, is essentially a predecessor of SPI and a trademark of [National Semiconductor](/source/National_Semiconductor). It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a [three-wire](#Three-wire) mode.

### Microwire/Plus

Microwire/Plus[31] is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

### JTAG

Main article: [JTAG](/source/JTAG)

Although there are some similarities between SPI and the [JTAG](/source/JTAG) (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable [test access to the I/O pins](/source/Boundary_scan) from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.[32]

## Development tools

### Single-board computers

[Single-board computers](/source/Single-board_computers) may provide [pin](/source/Lead_(electronics)) access to SPI hardware units. For instance, the [Raspberry Pi's J8 header](/source/Raspberry_Pi#J8_header_and_general_purpose_input-output_(GPIO)) exposes at least two SPI units that can be used via [Linux](/source/Linux) [drivers](/source/Device_driver) or [python](/source/Python_(programming_language)).

### USB to SPI adapters

There are a number of [USB](/source/USB) adapters that allow a desktop [PC](/source/Personal_computer) or [smartphone](/source/Smartphone) with [USB](/source/USB) to communicate with SPI chips (e.g. CH341A/B[33] based or [FT](/source/FTDI)221xs[34]). They are used for embedded systems, chips ([FPGA](/source/FPGA), [ASIC](/source/Application-specific_integrated_circuit), and [SoC](/source/System_on_a_chip)) and peripheral testing, programming and debugging. Many of them also provide scripting or programming capabilities (e.g. [Visual Basic](/source/Visual_Basic), [C](/source/C_(programming_language))/[C++](/source/C%2B%2B), [VHDL](/source/VHDL)) and can be used with open source programs like [flashrom](/source/Flashrom_(utility)), IMSProg, SNANDer or avrdude for [flash](/source/Flash_memory), [EEPROM](/source/EEPROM), [bootloader](/source/Bootloader) and [BIOS](/source/BIOS) programming.

The key SPI parameters are: the maximum supported frequency for the serial interface, command-to-command latency, and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length.

SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wire SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI[35]).

### Protocol analyzers

Main article: [Logic analyzer](/source/Logic_analyzer)

[Logic analyzers](/source/Logic_analyzers) are tools which collect, [timestamp](/source/Timestamp), analyze, decode, store, and view the high-speed waveforms, to help [debug](/source/Debugging) and develop. Most logic analyzers have the capability to decode SPI bus signals into high-level protocol data with human-readable labels.

#### Oscilloscopes

SPI [waveforms](/source/Waveforms) can be seen on [analog](/source/Analog_signal) channels (and/or via [digital](/source/Digital_signal) channels in [mixed-signal oscilloscopes](/source/Oscilloscope#Mixed-signal_oscilloscope)).[36] Most [oscilloscope](/source/Oscilloscope) vendors offer optional support for SPI protocol analysis (both 2-, [3-](#Three-wire), and 4-wire SPI) with triggering.

## Alternative terminology

Various alternative abbreviations for the four common SPI signals are used. (This section omits overbars indicating active-low.)

- Serial clock - SCK, SCLK, CLK, SCL

- Master Out Slave In (MOSI) - SIMO, MTSR, SPID - correspond to MOSI on both master and slave devices, connects to each other - SDI, DI, DIN, SI, SDA - on slave devices; various abbreviations for *serial data in*; connects to MOSI on master - SDO, DO, DOUT, SO - on master devices; various abbreviations for *serial data out*; connects to MOSI on slave - COPI, PICO for *peripheral* and *controller*,[37][38] or COTI for *controller* and *target*[39]

- Master In Slave Out (MISO) - SOMI, MRST, SPIQ - correspond to MISO on both master and slave devices, connects to each other - SDO, DO, DOUT, SO - on slave devices; connects to MISO on master - SDI, DI, DIN, SI - on master devices; connects to MISO on slave - CIPO, POCI,[37][38] or CITO[39]

- Slave Select (SS) - Chip select (CS) - CE (chip enable) - Historical: SSEL, NSS, /SS, SS#

[Microchip](/source/Microchip_Technology) uses *host* and *client* though keeps the abbreviation MOSI and MISO.[40]

## See also

- [Electronics portal](https://en.wikipedia.org/wiki/Portal:Electronics)

- [List of network buses](/source/List_of_network_buses)

## Notes

1. **[^](#cite_ref-1)** The earliest definitive mention of a "Serial Peripheral Interface" in bitsavers archives of Motorola manuals is from 1983 (see [§ Original definition](#Original_definition)). While some sources on the web allege that Motorola introduced SPI when 68000 was introduced in 1979, however many of those appear to be [citogenesis](/source/Citogenesis) or speculation, and Motorola's 1983 68000 manual has no mention of "Serial Peripheral Interface", so the alleged 1979 date does not seem to be reliable information. Please only add a specific design_date if you have a definitive source from Motorola around then.

1. **[^](#cite_ref-4)** Some slaves require a falling edge of the Slave Select signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.

1. ^ [***a***](#cite_ref-3wireSDI_9-0) [***b***](#cite_ref-3wireSDI_9-1) Not to be confused with the SDIO (Serial Data I/O) line of the half-duplex implementation of SPI sometimes also called "3-wire" SPI. Here e.g. MOSI (via a resistor) and MISO (no resistor) of a master is connected to the SDIO line of a slave.

1. **[^](#cite_ref-23)** Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. ([https://www.ti.com/product/OMAP3530](https://www.ti.com/product/OMAP3530))

1. **[^](#cite_ref-24)** Such as the SPI controller on Atmel AT91 chips like the at91sam9G20, which is much simpler than TI's McSPI.

## References

1. **[^](#cite_ref-:0_2-0)** Stoicescu, Alin (2018). ["Getting Started with SPI"](https://ww1.microchip.com/downloads/en/Appnotes/TB3215-Getting-Started-with-SPI-90003215A.pdf) (PDF). *[Microchip](/source/Microchip)*.

1. **[^](#cite_ref-3)** ["What is Serial Synchronous Interface (SSI)?"](https://digital.ni.com/public.nsf/allkb/862567530005F09C862566BE004E469D). Retrieved 2015-01-28.

1. ^ [***a***](#cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-0) [***b***](#cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-1) [***c***](#cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-2) [Better SPI Bus Design in 3 Steps](https://www.pjrc.com/better-spi-bus-design-in-3-steps/)

1. **[^](#cite_ref-6)** [SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.](https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf)

1. ^ [***a***](#cite_ref-:4_7-0) [***b***](#cite_ref-:4_7-1) ["AN991/D: Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"](https://www.nxp.com/docs/en/application-note/AN991.pdf) (PDF). *[NXP](/source/NXP)*. 2004 [1994]. [Archived](https://web.archive.org/web/20230404200636/https://www.nxp.com/docs/en/application-note/AN991.pdf) (PDF) from the original on 2023-04-04. Retrieved 2021-10-14.

1. **[^](#cite_ref-8)** ["TMS320x281x Serial Peripheral Interface Reference Guide"](https://www.ti.com/lit/pdf/spru059). *[Texas Instruments](/source/Texas_Instruments)*. 2002. pp. 16–17.

1. **[^](#cite_ref-10)** [Maxim-IC application note 3947: "Daisy-Chaining SPI Devices"](https://www.maximintegrated.com/en/app-notes/index.mvp/id/3947)

1. ^ [***a***](#cite_ref-:3_11-0) [***b***](#cite_ref-:3_11-1) Gammon, Nick (2013-03-23). ["Gammon Forum : Electronics : Microprocessors : Using a 74HC165 input shift register"](https://www.gammon.com.au/forum/?id=11979). *Gammon Forum*. [Archived](https://web.archive.org/web/20230729042912/http://www.gammon.com.au/forum/?id=11979) from the original on 2023-07-29. Retrieved 2023-08-03.

1. ^ [***a***](#cite_ref-:2_12-0) [***b***](#cite_ref-:2_12-1) Gammon, Nick (2012-01-31). ["Gammon Forum : Electronics : Microprocessors : Using a 74HC595 output shift register as a port-expander"](https://www.gammon.com.au/forum/?id=11518). *Gammon Forum*. [Archived](https://web.archive.org/web/20230714101259/http://www.gammon.com.au/forum/?id=11518) from the original on 2023-07-14. Retrieved 2023-08-03.

1. **[^](#cite_ref-13)** [*Interfaces*](https://books.google.com/books?id=8od7phxJHGkC), 1977, pp. 80, 84

1. **[^](#cite_ref-14)** ["Serial-Control Multiplexer Expands SPI Chip Selects"](https://web.archive.org/web/20190819062018/http://www.farnell.com/datasheets/312519.pdf) (PDF). *[Premier Farnell](/source/Premier_Farnell)*. 2001-07-01. Archived from [the original](http://www.farnell.com/datasheets/312519.pdf) (PDF) on 2019-08-19.

1. **[^](#cite_ref-15)** ["AVR910 - In-system programming"](https://web.archive.org/web/20110302123348/http://www.atmel.com/dyn/resources/prod_documents/DOC0943.PDF) (PDF). Archived from [the original](http://www.atmel.com/dyn/resources/prod_documents/DOC0943.PDF) (PDF) on 2011-03-02.

1. **[^](#cite_ref-16)** [*components :: motorola :: dataBooks :: 1983 Motorola 8-Bit Microprocessor and Peripheral Data*](http://archive.org/details/bitsavers_motorolada8BitMicroprocessorandPeripheralData_34048525).

1. **[^](#cite_ref-17)** [*motorola :: dataBooks :: 1984 Motorola Single-Chip Microcomputer Data*](http://archive.org/details/bitsavers_motoroladaSingleChipMicrocomputerData_68061538).

1. **[^](#cite_ref-18)** ["Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"](http://www.bitsavers.org/components/motorola/_appNotes/AN-0991_Using_the_Serial_Peripheral_Interface_to_Communicate_between_Multiple_Microcomputers.pdf) (PDF). *[Bitsavers](/source/Bitsavers)*.

1. **[^](#cite_ref-19)** [SafeSPI.org](http://SafeSPI.org)

1. **[^](#cite_ref-20)** ["Transmitting SPI over LVDS Interfaces"](https://www.ti.com/lit/ug/tidued8/tidued8.pdf?ts=1613343608107&ref_url=https%253A%252F%252Fwww.google.com%252F) (PDF). *Texas Instruments*. Retrieved 14 February 2021.

1. **[^](#cite_ref-21)** ["SPI Master Loopback Example"](https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v4.x.x/doc/html/group__spi__master__example.html). *Nordic Semiconductor*. Retrieved 14 February 2021.

1. **[^](#cite_ref-22)** ["Freescale Semiconductor, Inc. - QSM - Queued Serial Module - Reference Manual"](https://web.archive.org/web/20190824080750/https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf) (PDF). *[NXP](/source/NXP)*. 1996 [1991]. Archived from [the original](https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf) (PDF) on 2019-08-24.

1. **[^](#cite_ref-25)** ["Quad-SPI Brings Fast Parallel Data Transmission"](https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission). *[Cadence Design Systems](/source/Cadence_Design_Systems)*. 2023-01-11. [Archived](https://web.archive.org/web/20230601194620/https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission) from the original on 2023-06-01. Retrieved 2023-06-30.

1. ^ [***a***](#cite_ref-W25Q16JV_26-0) [***b***](#cite_ref-W25Q16JV_26-1) ["W25Q16JV 3V 16M-bit serial flash memory with Dual/Quad SPI"](https://www.winbond.com/resource-files/w25q16jv%20spi%20revd%2008122016.pdf) (PDF) (data sheet). Revision D. [Winbond](/source/Winbond). 12 August 2016. Retrieved 2017-02-10.

1. ^ [***a***](#cite_ref-D25LQ64_27-0) [***b***](#cite_ref-D25LQ64_27-1) [***c***](#cite_ref-D25LQ64_27-2) ["D25LQ64 1.8V Uniform Sector Dual and Quad SPI Flash"](https://web.archive.org/web/20170212090900/http://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf) (PDF) (data sheet). version 0.1. GigaDevice. 11 February 2011. Archived from [the original](https://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf) (PDF) on 12 February 2017. Retrieved 2017-02-10.

1. **[^](#cite_ref-28)** ["QuadSPI flash: Quad SPI mode vs. QPI mode"](https://community.nxp.com/thread/336422). *NXP community forums*. December 2014. Retrieved 2016-02-10.

1. **[^](#cite_ref-SST26VF032B_29-0)** ["SST26VF032B / SST26VF032BA 2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory"](http://ww1.microchip.com/downloads/en/DeviceDoc/20005218E.pdf) (PDF) (Data sheet). version E. [Microchip, Inc.](/source/Microchip%2C_Inc.) 2017. Retrieved 2017-02-10.

1. **[^](#cite_ref-30)** Patterson, David (May 2012). ["Quad Serial Peripheral Interface (QuadSPI) Module Updates"](https://web.archive.org/web/20160804162026/http://www.nxp.com/files/32bit/doc/app_note/AN4512.pdf) (PDF) (Application note). [Freescale Semiconductor](/source/Freescale_Semiconductor). Archived from [the original](https://www.nxp.com/files/32bit/doc/app_note/AN4512.pdf) (PDF) on August 4, 2016. Retrieved September 21, 2016.

1. **[^](#cite_ref-31)** Pell, Rich (13 October 2011). ["Improving performance using SPI-DDR NOR flash memory"](https://www.edn.com/design/systems-design/4368499/Improving-performance-using-SPI-DDR-NOR-flash-memory-4368499). *[EDN](/source/EDN_(magazine))*.

1. ^ [***a***](#cite_ref-eSPI_32-0) [***b***](#cite_ref-eSPI_32-1) [***c***](#cite_ref-eSPI_32-2) [***d***](#cite_ref-eSPI_32-3) [***e***](#cite_ref-eSPI_32-4) [***f***](#cite_ref-eSPI_32-5) [***g***](#cite_ref-eSPI_32-6) [***h***](#cite_ref-eSPI_32-7) [Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms)](https://www-ssl.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf) (PDF) (Report). Revision 1.0. Intel. January 2016. Document number 327432-004. Retrieved 2017-02-05.

1. **[^](#cite_ref-33)** [Enhanced Serial Peripheral Interface (eSPI) Interface Specification (for Client Platforms)](https://downloadmirror.intel.com/21353/eng/eSPI%20Specification%20rev0.6%20(client).pdf) (PDF) (Report). Revision 0.6. Intel. May 2012. Document Number 327432-001EN. Retrieved 2017-02-05.

1. **[^](#cite_ref-34)** ["Intel 100 Series Chipset Family PCH Datasheet, Vol. 1"](https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/100-series-chipset-datasheet-vol-1.pdf) (PDF). Retrieved April 15, 2015.

1. **[^](#cite_ref-35)** [MICROWIRE Serial Interface](https://www.ti.com/lit/an/snoa743/snoa743.pdf) National Semiconductor Application Note AN-452

1. **[^](#cite_ref-36)** [MICROWIRE/PLUS Serial Interface for COP800 Family](https://www.ti.com/lit/an/snoa093/snoa093.pdf) National Semiconductor Application Note AN-579

1. **[^](#cite_ref-37)** IEEE 1149.1-2013

1. **[^](#cite_ref-38)** ["USB Bridge Controller CH341 with UART, SPI and I2C"](https://wch-ic.com/products/CH341.html). *WCH*. Retrieved 27 February 2025.

1. **[^](#cite_ref-39)** ["USB to SPI converter"](https://ftdichip.com/products/ft221xs/). *FTDI*. 2 August 2020. Retrieved 14 February 2021.

1. **[^](#cite_ref-40)** [SPI Storm – Serial Protocol Host Adapter](https://www.byteparadigm.com/product-spi-storm-39.html) with support of custom serial protocols, Byte Paradigm.

1. **[^](#cite_ref-41)** ["N5391B I²C and SPI Protocol Triggering and Decode for Infiniium scopes"](https://www.keysight.com/en/pd-1646694-pn-N5391B/ic-and-spi-protocol-triggering-and-decode?cc=US&lc=eng).

1. ^ [***a***](#cite_ref-OSHWA_42-0) [***b***](#cite_ref-OSHWA_42-1) ["SPI; OSHWA"](https://web.archive.org/web/20210127234925/https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names). Archived from [the original](https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/) on 2021-01-27. Retrieved 2023-06-02.

1. ^ [***a***](#cite_ref-:5_43-0) [***b***](#cite_ref-:5_43-1) ["Product Overview - Translate Voltages for SPI"](https://web.archive.org/web/20220317120519/https://www.ti.com/lit/an/scea091a/scea091a.pdf) (PDF). Archived from [the original](https://www.ti.com/lit/an/scea091a/scea091a.pdf) (PDF) on 2022-03-17.

1. ^ [***a***](#cite_ref-:1_44-0) [***b***](#cite_ref-:1_44-1) ["Serial Peripheral Interface (SPI) Devices"](https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/www.nxp.com/pages/:SPI). *[NXP](/source/NXP)*. [Archived](https://web.archive.org/web/20230601020101/https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/spi-interface-devices:SPI) from the original on 2023-06-01. Retrieved 2023-07-22.

1. **[^](#cite_ref-45)** Stoicescu, Alin. ["Getting Started with Serial Peripheral Interface (SPI)"](https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html). *[Microchip Technology](/source/Microchip_Technology)*. [Archived](https://web.archive.org/web/20231221205244/https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html) from the original on 2023-12-21. Retrieved 2023-12-21.

## External links

Wikimedia Commons has media related to [Serial Peripheral Interface](https://commons.wikimedia.org/wiki/Category:Serial_Peripheral_Interface).

- [Intel eSPI (Enhanced Serial Peripheral Interface)](https://www.intel.com/content/www/us/en/support/software/chipset-software/000020952.html)

- [SPI Tutorial](https://www.corelis.com/education/SPI_Tutorial.htm)

v t e Technical and de facto standards for wired computer buses General System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play Double data rate Quad data rate List of bus bandwidths Standards SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire Storage ST-506 ESDI SDI IPI SMD Floppy connector Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface) Peripheral Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt CAN bus Audio ADAT Lightpipe AES3 Intel HD Audio I2S MADI McASP S/PDIF TOSLINK Portable PC Card ExpressCard Embedded Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category

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Adapted from the Wikipedia article [Serial Peripheral Interface](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.