# Scalar processor

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Class of computer processors

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**Scalar processors** are a class of [computer processors](/source/Computer_processor) that process only one data item at a time. Typical data items include [integers](/source/Integer_(computer_science)) and [floating point numbers](/source/Floating_point_number).[1]

## Classification

A scalar processor is classified as a single instruction, single data ([SISD](/source/Single_instruction%2C_single_data)) processor in [Flynn's taxonomy](/source/Flynn's_taxonomy). The [Intel 486](/source/I486) is an example of a scalar processor. It is to be contrasted with a [vector processor](/source/Vector_processor) where a single instruction operates simultaneously on multiple data items (and thus is referred to as a single instruction, multiple data ([SIMD](/source/Single_instruction%2C_multiple_data)) processor).[2] The difference is analogous to the difference between [scalar](/source/Scalar_(mathematics)) and [vector](/source/Vector_(geometric)) arithmetic.

The term *scalar* in computing dates to the 1970 and 1980s when vector processors were first introduced. It was originally used to distinguish the older designs from the new vector processors.

## Superscalar processor

A [superscalar](/source/Superscalar) processor (such as the [Intel P5](/source/P5_(microarchitecture))) may execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.[1] The [Cortex-M7](/source/Cortex-M7), like many consumer [CPUs](/source/Central_processing_unit) today, is a superscalar processor.[3]

## Scalar data type

A scalar data type, or just **scalar**, is any non-[composite](/source/Object_composition) [value](/source/Value_(computer_science)).

Generally, all basic [primitive data types](/source/Primitive_data_type) are considered scalar:

- The [Boolean data type](/source/Boolean_data_type) (bool)

- Numeric types ([int](/source/Integer_(computer_science)), the [floating point](/source/Floating_point) types float and double)

- Character types ([char](/source/Character_(computer_science)#char))

Some programming languages also treat [strings](/source/String_(computer_science)) as scalar types, while other languages treat strings as [arrays](/source/Array_(data_structure)) or [objects](/source/Object_(computer_science)).

## See also

- [Instruction pipeline](/source/Instruction_pipeline)

- [Parallel computing](/source/Parallel_computing)

## References

1. ^ [***a***](#cite_ref-Ram_2001_p._11_1-0) [***b***](#cite_ref-Ram_2001_p._11_1-1) Ram, Badri (2001). *Advanced microprocessors and interfacing*. New Delhi: Tata McGraw-Hill Pub. Co. p. 11. [ISBN](/source/ISBN_(identifier)) [978-0-07-043448-6](https://en.wikipedia.org/wiki/Special:BookSources/978-0-07-043448-6). [OCLC](/source/OCLC_(identifier)) [55946893](https://search.worldcat.org/oclc/55946893).

1. **[^](#cite_ref-Patterson_2012_p._650_2-0)** Patterson, David (2012). *Computer organization and design: the hardware/software interface*. Waltham, MA: Morgan Kaufmann. p. 650. [ISBN](/source/ISBN_(identifier)) [978-0-12-374750-1](https://en.wikipedia.org/wiki/Special:BookSources/978-0-12-374750-1). [OCLC](/source/OCLC_(identifier)) [746618653](https://search.worldcat.org/oclc/746618653).

1. **[^](#cite_ref-3)** ["Cortex-M7"](https://developer.arm.com/ip-products/processors/cortex-m/cortex-m7). *Arm Developer*. Arm Limited. Retrieved 2021-07-03.

v t e Processor technologies Models Abstract machine Stored-program computer Finite-state machine with datapath Hierarchical Deterministic finite automaton Queue automaton Cellular automaton Quantum cellular automaton Turing machine Alternating Turing machine Universal Post–Turing Quantum Nondeterministic Turing machine Probabilistic Turing machine Hypercomputation Zeno machine Belt machine Stack machine Register machines Counter Pointer Random-access Random-access stored program Architecture Microarchitecture Von Neumann Harvard modified Dataflow Transport-triggered Cellular Endianness Memory access NUMA HUMA Load–store Register/memory Cache hierarchy Memory hierarchy Virtual memory Secondary storage Heterogeneous Fabric Multiprocessing Cognitive Neuromorphic Instruction set architectures Types Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes Instruction sets Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False sharing Out-of-order Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue Speculative Branch prediction Memory dependence prediction Parallelism Level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed Multithreading Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD Processor performance Transistor count Instructions per cycle (IPC) Cycles per instruction (CPI) Instructions per second (IPS) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic updates per second (SUPS) Performance per watt (PPW) Cache performance metrics Computer performance by orders of magnitude Types Central processing unit (CPU) Graphics processing unit (GPU) GPGPU Vector Barrel Stream Tile processor Coprocessor PAL ASIC FPGA FPOA CPLD Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP) By application Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor Systems on chip System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC) Hardware accelerators Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor Word size 1-bit 4-bit 8-bit 12-bit 15-bit 16-bit 24-bit 32-bit 48-bit 64-bit 128-bit 256-bit 512-bit bit slicing others variable Core count Single-core Multi-core Manycore Heterogeneous architecture Components Core Cache CPU cache Scratchpad memory Data cache Instruction cache replacement policies coherence Bus Clock rate Clock signal FIFO Functional units Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder Logic Combinational Sequential Glue Logic gate Quantum Array Registers Processor register Status register Stack register Register file Memory buffer Memory address register Program counter Control unit Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter Datapath Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter Circuitry Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch Power management PMU APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Performance per watt (PPW) Related History of general-purpose CPUs Microprocessor chronology Processor design Digital electronics Hardware security module Semiconductor device fabrication Tick–tock model Pin grid array Chip carrier

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