# PowerPC 600

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{{Short description|Family of PowerPC processors}}
{{More citations needed|date=May 2023}}
The '''PowerPC 600''' family was the first family of [PowerPC](/source/PowerPC) [processors](/source/microprocessor) built. They were designed at the Somerset facility in [Austin, Texas](/source/Austin%2C_Texas), jointly funded and staffed by engineers from [IBM](/source/IBM) and [Motorola](/source/Motorola) as a part of the [AIM alliance](/source/AIM_alliance). Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for [personal computer](/source/personal_computer)s. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

{{POWER, PowerPC, and Power ISA}}

==Nuclear family==
{| class="wikitable"
|-
!CPU
!Pipeline stages
!Features
|-
|PowerPC 601
|4
|3 execution units, static branch prediction. SMP support.
|-
|PowerPC 603
|4
|5 execution units, branch prediction. No SMP.
|-
|PowerPC 604
|6
|Superscalar, out-of-order execution, 6 execution units. SMP support.
|-
|PowerPC 620
|5
|Out-of-order execution- SMP support.
|}

===PowerPC 601===
thumb|left|The PowerPC 601 prototype reached first silicon in October 1992.

The '''PowerPC 601''' was the first generation of microprocessors to support the basic [32-bit](/source/32-bit) [PowerPC](/source/PowerPC) [instruction set](/source/instruction_set). The design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992. The first 601 processors were introduced in an IBM [RS/6000](/source/RS%2F6000) [workstation](/source/workstation) in October 1993 (alongside its more powerful multichip cousin [IBM](/source/IBM) [POWER2](/source/POWER2) line of processors) and the first Apple [Power Macintosh](/source/Power_Macintosh)es on March 14, 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an extremely aggressive schedule while including substantially new functionality (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first [symmetric multiprocessing](/source/symmetric_multiprocessing) (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBM [RISC Single Chip](/source/RISC_Single_Chip) (RSC) processor,<ref>{{cite web|url=https://arstechnica.com/features/2004/08/ppc-1/2/|title=PowerPC on Apple: An Architectural History, Part I (page 2, "PowerPC 601")|first1=Jon|last1=Stokes|date=August 3, 2004|publisher=[Ars Technica](/source/Ars_Technica)}}</ref> but also included support for the vast majority of the new PowerPC instructions not in the [POWER instruction set](/source/IBM_POWER_Instruction_Set_Architecture). While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unified [I/O](/source/I%2FO) [bus](/source/Bus_(computing)) structure and SMP/[memory coherency](/source/memory_coherency) support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning. Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM and software developers in their transitions to PowerPC. From start of design to [tape-out](/source/tape-out) of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.

====60x bus====
In order to help the effort to rapidly incorporate the [88110](/source/88110) bus architecture to the 601 for the benefit of the alliance and its customers, Motorola management provided not only the 88110 bus architecture specifications, but also a handful of 88110 bus-literate designers to help with the 60x bus logic implementation and verification. Given the Apple system design team was familiar with the I/O bus structure from Motorola's 88110 and this I/O bus implementation was well defined and documented, the 601 team adopted the bus technology to improve time to market. The bus was renamed the '''60x bus''' once implemented on the 601.<ref>{{cite web|url=http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF7785256996007248B1/$file/60xbus.pdf|title=The Bus Interface for 32-Bit Microprocessors|publisher=[Motorola](/source/Motorola)|year=1997}}</ref> These Motorola (and a small number of Apple) designers joined over 120 IBM designers in creating the 601.

Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their support [ASIC](/source/Application-specific_integrated_circuit)s and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses had not been adopted).
Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.

This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604, [G3](/source/PowerPC_7xx), [G4](/source/PowerPC_G4) and Motorola/Freescale [PowerQUICC](/source/PowerQUICC) processors.

thumb|An 80 MHz PowerPC 601

====Design====
The chip was designed to suit a wide variety of applications and had support for external [L2 cache](/source/CPU_cache) and [symmetric multiprocessing](/source/symmetric_multiprocessing). It had four functional units, including a [floating-point unit](/source/floating-point_unit), an [integer unit](/source/arithmetic_logic_unit), a branch unit and a sequencer unit. The processor also included a [memory management unit](/source/memory_management_unit). The integer [pipeline](/source/Instruction_pipeline) was four stages long, the branch pipeline two stages long, the memory pipeline five stages long, and the floating-point pipeline six stages long.

First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and by Motorola as the MPC601. It operated at speeds ranging from 50 to 80&nbsp;MHz. It was fabricated using a 0.6&nbsp;μm [CMOS](/source/CMOS) process with four levels of [aluminum interconnect](/source/aluminum_interconnect). The die was 121&nbsp;mm<sup>2</sup> large and contained 2.8 million transistors. The 601 has a 32&nbsp;KB unified [L1 cache](/source/CPU_cache), a capacity that was considered large at the time for an on-chip cache. Thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competing [Intel](/source/Intel) [Pentium](/source/P5_(microarchitecture)). The PowerPC 601 was used in the first [Power Macintosh](/source/Power_Macintosh) computers from [Apple](/source/Apple_Inc.), and in a variety of [RS/6000](/source/RS%2F6000) workstations and SMP servers from IBM and [Groupe Bull](/source/Groupe_Bull).

IBM was the sole manufacturer of the 601 and 601+ microprocessors in its [Burlington, Vermont](/source/Burlington%2C_Vermont) and [East Fishkill, New York](/source/East_Fishkill%2C_New_York) production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola. These facts are somewhat obscured given there are various pictures of the "Motorola MPC601", particularly one specific case of masterful Motorola marketing where the 601 was named one of ''[Time Magazine](/source/Time_(magazine))''{{'}}s 1994 "Products of the Year" with a Motorola marking.

* [https://m.youtube.com/watch?v=BRoS_m1g1_Q PowerPC 601 Microprocessor, lecture by Keith Diefendorff]

====PowerPC 601v====<!-- This section is linked from [List of Macintosh models grouped by CPU type](/source/List_of_Macintosh_models_grouped_by_CPU_type) -->
thumb|left|An IBM manufactured 90&nbsp;MHz PowerPC 601v. Notice the slightly smaller die.

An updated version, the '''PowerPC 601v''' or '''PowerPC 601+''', operating at 90 to 120&nbsp;MHz was introduced in 1994. It was fabricated in a newer 0.5&nbsp;μm CMOS process with four levels of interconnect, resulting in a die measuring 74&nbsp;mm<sup>2</sup>. The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBM [EDA tools](/source/Electronic_design_automation) on IBM systems and were fabricated in IBM-only facilities.<ref>{{cite conference|last1=Allen|first1=M.|last2=Becker|first2=M|date=February 1993|title=Multiprocessing Aspects of the PowerPC 601 Microprocessor|conference=Compcon|pages=117&ndash;126}}</ref><ref>{{cite journal|last1=Becker|first1=Michael K.|date=September 1993|title=The PowerPC 601 Microprocessor|journal=IEEE Micro|volume=13 |issue=5 |pages=54&ndash;68|doi=10.1109/40.238002 |s2cid=26895845 |display-authors=etal |bibcode=1993IMicr..13e..54B }}</ref><ref>{{cite conference|last1=Moore|first1=C.R.|date=February 1993|title=The PowerPC 601 Microprocessor|conference=Compcon|pages=109&ndash;116}}</ref><ref>{{cite web|url=http://www-03.ibm.com/systems/p/hardware/whitepapers/power/ppc_601.html|title= PowerPC 601 Microprocessor|archive-url=https://web.archive.org/web/20090207004025/http://www-03.ibm.com/systems/p/hardware/whitepapers/power/ppc_601.html|archive-date=February 7, 2009}}</ref>

===PowerPC 603===
[[Image:XPC603EFE100LF 01.jpg|thumb|A 100 MHz Motorola PowerPC 603 in a [wire bond](/source/Wire_bonding) [Quad Flat Package](/source/Quad_flat_package) ]]

The '''PowerPC 603''' was the first processor implementing the complete 32-bit [PowerPC Architecture](/source/PowerPC) as specified. Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2&nbsp;W and a small die of 85&nbsp;mm<sup>2</sup>.<ref>Pham et al., "A 3.0 W 75 SPECint92 85 SPECfp92 Superscalar RISC Microprocessor", ''ISSC Digest Of Technical Papers'', pp. 212–213, Feb. 1994.</ref><ref>Burgess et al., "The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", ''Proceedings of COMPCON '94'', Feb. 1994.</ref><ref>Gary et al., "The PowerPC 603 Microprocessor: A Low-Power Design For Portable Applications", ''Proceedings of COMPCON '94'', Feb. 1994.</ref><ref name=603_gerosa>Gerosa et al., "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", ''IEEE Journal of Solid-State Circuits'', vol. 29, pp. 1440–1454, Dec. 1994.</ref> It was designed to be a low cost, low power processor for portable applications. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2&nbsp;mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating-point unit, [branch prediction unit](/source/branch_predictor), load/store unit and a system registry unit. It has separate 8&nbsp;KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120&nbsp;MHz at 3.8 V.<ref name=603_gerosa/> The 603 core did not have hardware support for [SMP](/source/symmetric_multiprocessing).

[[Image:XPC603PRX200LC 01.jpg|thumb|left|A 200 MHz Motorola PowerPC 603 in a ceramic [Ball Grid Array](/source/Ball_Grid_Array) packaging]]

The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5&nbsp;μm CMOS process with four levels of interconnect. The die was 85&nbsp;mm<sup>2</sup> large drawing 2.2&nbsp;W at 80&nbsp;MHz.<ref name=603_gerosa /><ref>{{cite web|url=http://www.chips.ibm.com/products/ppc/documents/papers/603.html |title=PowerPC 603 Microprocessor |author1=James Kahle |author2=Deene Ogden |publisher=IBM |url-status=dead |archive-url=https://web.archive.org/web/19970806001650/http://www.chips.ibm.com/products/ppc/documents/papers/603.html |archive-date=August 6, 1997 }}</ref> The 603 architecture is the direct ancestor to the [PowerPC 750](/source/PowerPC_7xx) architecture, marketed by Apple as the PowerPC "G3".

The 603 was intended to be used for portable [Apple Macintosh computers](/source/List_of_Macintosh_models_grouped_by_CPU) but could not run [68K emulation software](/source/Mac_68k_emulator) with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line.<ref>{{cite magazine|url=https://pdfs.semanticscholar.org/9492/040bfd1226a08b25c92539fe4d724d01a5dc.pdf|archive-url=https://web.archive.org/web/20180730110252/https://pdfs.semanticscholar.org/9492/040bfd1226a08b25c92539fe4d724d01a5dc.pdf|url-status=dead|archive-date=July 30, 2018|title=Arthur Revitalizes PowerPC Line|author=Linley Gwennap|magazine=[Microprocessor Report](/source/Microprocessor_Report)|volume=11|issue=2|date=February 27, 1997|s2cid=51808955 |quote=The 603’s tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e’s caches cause a significant performance hit at higher clock speeds. Given Arthur’s design target of 250 MHz and up, doubling the caches again made sense.}}</ref><ref>{{cite web |url=http://lowendmac.com/2014/cpus-powerpc-603-and-603e/ |title=CPUs: PowerPC 603 and 603e |last=Jansen |first=Daniel |date=2014 |publisher=Low End Mac |access-date=29 July 2018}}</ref> This caused the delay of the Apple [PowerBook 5300](/source/PowerBook_5300) and [PowerBook Duo 2300](/source/PowerBook_Duo), as Apple chose to wait for a processor revision. Apple's use of the 603 in the [Performa 5200](/source/Performa_5200) line led to the processor getting a poor reputation. Aside from the issue of 68K emulation performance, the Performa machines shipped with a variety of design flaws, some of them severe, related to other aspects of the computers' design, including networking performance and stability, bus problems (width, speed, contention, and complexity), ROM bugs, and hard disk performance.<ref>{{cite web |url=http://lowendmac.com/1997/performa-and-power-mac-x200-issues/ |title=Performa and Power Mac x200 Issues |last=Barber |first=Scott |date=1997 |publisher=Low End Mac |access-date=29 July 2018}}</ref><ref>{{cite web |url=http://www.insanely-great.com/features/010806.html |title=The 10 Worst Macs Ever Built |last=Davison |first=Remy |publisher=Insanely Great Mac |url-status=dead |archive-url=https://web.archive.org/web/20100201100435/http://www.insanely-great.com/features/010806.html |archive-date=February 1, 2010 |access-date=July 30, 2018 }}</ref> None of the problems of the 5200 line, aside from 68K emulation performance, were inherently due to the 603. Rather, the processor was retrofitted to be used with 68K motherboards and other obsolete parts.<ref>{{cite web |url=http://lowendmac.com/2014/power-mac-and-performa-x200-road-apples/ |last=Knight |first=Daniel |title=Power Mac and Performa x200, Road Apples |date=2014 |publisher=Low End Mac |access-date=29 July 2018}}</ref> The site Low End Mac rates the Performa 5200 as the worst Mac of all-time.<ref>{{cite web |url=http://lowendmac.com/1995/performa-5200/ |title=Performa 5200 |date=1995 |publisher=Low End Mac |access-date=29 July 2018}}</ref> The 603 found widespread use in different embedded appliances.{{Citation needed|date=July 2018}}
{{anchor|603e_and_603ev}}
====PowerPC 603e and 603ev====
right|thumb|180px|IBM PPC603ev, 200&nbsp;MHz

The performance issues of the 603 were addressed in the '''PowerPC 603e'''. The L1 cache was enlarged and enhanced to 16&nbsp;KB four-way set-associative data and instruction caches. The clock speed of the processors was doubled too, reaching 200&nbsp;MHz. Shrinking the fabrication process to 350&nbsp;nm allowed for speeds of up to 300&nbsp;MHz. This part is sometimes called '''PowerPC 603ev'''. The 603e and 603ev have 2.6 million transistors each and are 98&nbsp;mm<sup>2</sup> and 78&nbsp;mm<sup>2</sup> large respectively. The 603ev draws a maximum of 6&nbsp;W at 300&nbsp;MHz.<ref>{{cite web|url=http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC603E|title=Freescale's 603e page|publisher=[Freescale Semiconductor](/source/Freescale_Semiconductor)}}</ref><ref>{{cite web|url=http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_603e_Microprocessor |title=IBM's 603e page |url-status=dead |archive-url=https://web.archive.org/web/20090207004411/http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_603e_Microprocessor |archive-date=February 7, 2009 }}</ref>

The PowerPC 603e was the first mainstream desktop processor to reach 300&nbsp;MHz, as used in the [Power Macintosh 6500](/source/Power_Macintosh_6500). The 603e was also used in accelerator cards from [Phase5](/source/Phase5) for the [Amiga](/source/Amiga) line of computers, with CPUs ranging in speeds from 160 to 240&nbsp;MHz. The PowerPC 603e is still sold today by IBM and Freescale, and others like [Atmel](/source/Atmel) and [Honeywell](/source/Honeywell) who makes the [radiation hardened](/source/radiation_hardened) variant [RHPPC](/source/RHPPC). The PowerPC 603e was also the heart of the [BeBox](/source/BeBox) from [Be Inc.](/source/Be_Inc.) The BeBox is notable since it is a [multiprocessing](/source/multiprocessing) system, something the 603 was not designed for. IBM also used PowerPC 603e processors in the [IBM ThinkPad 800 series](/source/IBM_ThinkPad_800_series). In certain digital oscilloscope series, [LeCroy](/source/LeCroy_Corporation) used the PowerPC 603e as the main processor.<ref>LeCroy 1998 Test & Measurement Products Catalog, TMCAT98 0498</ref><ref>LeCroy 2001 Test and Measurement Products Catalog</ref> The 603e processors also power all 66 [satellites](/source/Iridium_(satellite)) in the [Iridium](/source/Iridium_Satellite_LLC) satellite phone fleet. The satellites each contain seven Motorola/Freescale PowerPC 603e processors running at roughly 200&nbsp;MHz each. A custom 603e processor is also used in the [Mark 54 Lightweight Torpedo](/source/Mark_54_Lightweight_Torpedo).

====G2====
The PowerPC 603e core, renamed '''G2''' by [Freescale](/source/Freescale), is the basis for many embedded [PowerQUICC II](/source/PowerQUICC) processors, and, as such, it keeps on being developed. Freescale's PowerQUICC II [SoC](/source/System-on-a-chip) processors bear the designation MPC82xx, and come in a variety of configurations reaching 450&nbsp;MHz. The G2 name is also used as a retronym for the 603e and 604 processors to align with the G3, G4, and the G5.

====e300====
{{Main|PowerPC e300}}

Freescale has enhanced the 603e core, calling it '''e300''', in the [PowerQUICC II Pro](/source/PowerQUICC) embedded processors. Larger 32/32&nbsp;KB L1 caches and other performance enhancing measures were added. Freescale's PowerQUICC II Pro [SoC](/source/System-on-a-chip) processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667&nbsp;MHz. The e300 is also the core of the [MPC5200B](/source/PowerPC_5000) SoC processor that is used in the small [EFIKA](/source/EFIKA) computer.

===PowerPC 604===
[[Image:Motorola PowerPC 604e 233MHz 2.jpg|thumb|A 233 MHz Motorola PowerPC 604e mounted on a [Phase5](/source/Phase5) CyberstormPPC processor card for the Commodore [Amiga 4000](/source/Amiga_4000) series computers]]

The '''PowerPC 604''' was introduced in December 1994 alongside the 603 and was designed as a high-performance chip for [workstation](/source/workstation)s and entry-level servers and as such had support for [symmetric multiprocessing](/source/symmetric_multiprocessing) in hardware. The 604 was used extensively in [Apple](/source/Apple_Inc.)'s high-end systems and was also used in [Macintosh clone](/source/Macintosh_clone)s, IBM's low-end [RS/6000](/source/RS%2F6000) servers and workstations, [Amiga](/source/Amiga) accelerator boards, and as an embedded CPU for telecom applications.

The 604 is a [superscalar](/source/superscalar) processor capable of issuing four instructions simultaneously. The 604 has a six-stage pipeline and six execution units that can work in parallel, finishing up to six instructions every cycle. It has two simple and one complex [integer units](/source/arithmetic_logic_unit), one [floating-point unit](/source/floating-point_unit), one branch-processing unit managing [out-of-order execution](/source/out-of-order_execution), and one load/store unit. It has separate 16&nbsp;KB data and instruction L1 caches. The external interface is a 32- or 64-bit 60x bus that operates at clock rates up to 50&nbsp;MHz.

The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5&nbsp;μm CMOS process with four levels of interconnect. The die measured 12.4&nbsp;mm by 15.8&nbsp;mm (196&nbsp;mm<sup>2</sup>) and drew 14-17&nbsp;W at 133&nbsp;MHz. It operated at speeds between 100 and 180&nbsp;MHz.<ref>{{cite web|url=https://arstechnica.com/articles/paedia/cpu/ppc-1.ars/6|title=PowerPC on Apple: An Architectural History, Part I (page 6, The PowerPC 604)|first1=Jon|last1=Stokes|date=August 3, 2004|publisher=Ars Technica}}</ref><ref>{{cite journal|url=https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/080501.pdf|last1=Gwennap|first1=Linley|date=April 18, 1994|title=PPC 604 Powers Past Pentium|journal=[Microprocessor Report](/source/Microprocessor_Report)|volume=8|issue=5}}</ref><ref>{{cite journal|last1=Song|first1=Peter S.|last2=Denman|first2=Marvin|last3=Chang|first3=Joe|date=October 1994|title=The PowerPC 604 RISC Microprocessor|journal=[IEEE Micro](/source/IEEE_Micro)|volume=14 |issue=5 |page=8 |doi=10.1109/MM.1994.363071 |bibcode=1994IMicr..14e...8S |s2cid=11603864 }}</ref>

* [https://m.youtube.com/watch?v=Vm0itpIc80g Power PC 604 RISC microprocessor, lecture by Marvin Denman]

====PowerPC 604e====
[[Image:IBM PPC604e 200.jpg|thumb|left|A 200 MHz IBM PowerPC 604e processor on the CPU module of an [Apple Network Server 700](/source/Apple_Network_Server) ]]

The '''PowerPC 604e''' was introduced in July 1996 and added a condition register unit and separate 32&nbsp;KB data and instruction L1 caches among other changes to its memory subsystem and branch prediction unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35&nbsp;μm CMOS process with five levels of interconnect. The die was 148&nbsp;mm<sup>2</sup> or 96&nbsp;mm<sup>2</sup> large, manufactured by Motorola and IBM respectively, drawing 16–18&nbsp;W at 233&nbsp;MHz. It operated at speeds between 166 and 233&nbsp;MHz and supported a memory bus up to 66&nbsp;MHz.<ref>{{cite web|url=http://www.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_604e_Microprocessor |title=IBM's PowerPC 604e page |website=[IBM](/source/IBM) }}{{dead link|date=July 2020|bot=medic}}{{cbignore|bot=medic}}</ref><ref>{{cite web|url=http://www.nxp.com/pages/microprocessor:MPC604E? |title=NXP's PowerPC 604e page}}</ref>

====PowerPC 604ev "Mach5"====
The '''PowerPC 604ev''', '''604r''' or '''"Mach 5"''' was introduced in August 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption. The die was 47&nbsp;mm<sup>2</sup> small manufactured on a 0.25&nbsp;μm CMOS process with five levels of interconnect, and drew 6&nbsp;W at 250&nbsp;MHz. It operated at speeds between 250 and 400&nbsp;MHz and supported a memory bus up to 100&nbsp;MHz.

While Apple dropped the 604ev in 1998 in favor for the [PowerPC 750](/source/PowerPC_750), IBM kept using it in entry-level models of its [RS/6000](/source/RS%2F6000) computers for several years.

===PowerPC 620===<!-- This section is linked from [64-bit](/source/64-bit) -->
The '''PowerPC 620''' was the first implementation of the entire [64-bit](/source/64-bit) PowerPC architecture. It was a second generation PowerPC alongside the 603 and 604, but geared towards the high-end workstation and server market. It was powerful on paper and was initially supposed to be launched alongside its brethren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e surpassed it.<ref>{{cite web |url=https://techmonitor.ai/technology/ibm_trashes_powerpc_620_system_plans_1 |title=IBM trashes PowerPC 620 system plans |author=<!--CBR Staff Writer--> |date=August 25, 1997 |website=Tech Monitor |publisher=New Statesman Media Group Ltd. |access-date=March 20, 2021}}</ref> The 620 was therefore never produced in large quantities and found very little use. The sole user of PowerPC 620 was [Groupe Bull](/source/Groupe_Bull) in its Escala [UNIX](/source/UNIX) machines, but they did not deliver any large numbers. IBM, which intended to use it in workstations and servers, decided to wait for the even more powerful [RS64](/source/RS64) and [POWER3](/source/POWER3) 64-bit processors instead.

The 620 was produced by Motorola in a 0.5&nbsp;μm process. It had 6.9 million transistors and the die had an area of 311&nbsp;mm<sup>2</sup>. It operated at clock rates between 120 and 150&nbsp;MHz, and drew 30&nbsp;W at 133&nbsp;MHz. A later model was built using a 0.35&nbsp;μm process, enabling it to reach 200&nbsp;MHz.{{Explain|date=July 2018}}

The 620 was similar to the 604. It has a five-stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units.<ref>{{cite book |last1=Shen |first1=John Paul |last2=Lipasti |first2=Mikko H. |title=Modern processor design: fundamentals of superscalar processors |date=2013 |publisher=Waveland Press |location=Long Grove, Illinois |isbn=978-1-4786-0783-0 |pages=302–303 |edition=Reissued}}</ref> With larger 32&nbsp;KB instruction and data caches, support for a L2 cache that may have a capacity of 128&nbsp;[MB](/source/Megabyte), and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604. The floating-point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instructions in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.{{Explain|date=July 2018}}

====6XX, MX, and future buses====
The system bus was a wider and faster 128-bit memory bus called the '''6XX bus'''. It was designed to be a system bus for multiprocessor systems where processors, caches, memory and I/O was to be connected, assisted by a system control chip. It supports both 32- and 64-bit PowerPC processors, memory addresses larger than 32&nbsp;bits, and [NUMA](/source/Non-Uniform_Memory_Access) environments. It was also used in POWER3, RS64, as well as 604-based RS/6000 systems (with the "Orca" bridge chip<ref>{{cite web|title=The Orca Chip...Heart of IBM's RISC System/6000 "Value" Servers|url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S1/HC8.1.3.pdf}}</ref>).<ref>{{cite web|url=http://www.byte.com/art/9411/sec8/art5.htm|title=PowerPC 620 Soars|first1=Tom|last1=Thompson|first2=Bob|last2=Ryan|publisher=Byte|archive-url=https://web.archive.org/web/19961220034942/http://www.byte.com/art/9411/sec8/art5.htm|archive-date=December 20, 1996}}</ref> 

The MX IO but was utilized for IO connection in 6xx based systems. The chipsets (initially named after snakes) featured bridges between the 6xx and MX bus, with additional chips to bridge between the MX and standard IO busses.

The 6XX bus later evolved into a distributed coherent bus refereed to as the '''Fabric Bus''', while the '''MX''' bus evolved into the '''GX bus'''(The G in reference to the project codename GigaProcessor), both utilized in the [POWER4](/source/POWER4). Later '''GX+''' and '''GX++''' in [POWER5](/source/POWER5) and [POWER6](/source/POWER6) respectively. The GX bus is also used in IBM's [z10](/source/IBM_System_z10) and [z196](/source/IBM_zEnterprise_System) [System z](/source/IBM_System_z) mainframes.
*[http://www.feb-patrimoine.com/Histoire/temoignages/histoire_unix_chez_bull_12_2004.pdf Contribution to the history of Unix at Bull] (Interesting reading concerning the use of PowerPC 620 at Bull. In French)

==Extended family==
thumb|Die shot of Motorola PowerPC 603

===PowerPC 602===
The '''PowerPC 602''' was a stripped-down version of PowerPC 603, specially made for game consoles by Motorola and IBM, introduced in February 1995.<ref name="NGen6">{{cite journal|title=M2 |journal=[Next Generation](/source/Next_Generation_(magazine))|issue=6|publisher=[Imagine Media](/source/Imagine_Media)|date=June 1995|pages=36–40}}</ref> It has smaller L1 caches (4&nbsp;KB instruction and 4&nbsp;KB data), a single-precision floating-point unit<ref name="NGen6"/> and a scaled back branch prediction unit. It was offered at speeds ranging from 50 to 80&nbsp;MHz, and drew 1.2&nbsp;W at 66&nbsp;MHz. It consisted of 1 million transistors and it was 50&nbsp;mm<sup>2</sup> large manufactured in a 0.5&nbsp;μm, CMOS process with four levels of interconnect.<ref>{{Cite web |url=http://www.nxp.com/files/32bit/doc/data_sheet/MPC602EC.pdf |title=PowerPC 602 RISC Microprocessor Hardware Specification |access-date=2016-07-24 |archive-date=2016-08-07 |archive-url=https://web.archive.org/web/20160807080653/http://www.nxp.com/files/32bit/doc/data_sheet/MPC602EC.pdf |url-status=dead }}</ref>

[3DO](/source/The_3DO_Company) developed the [M2 game console](/source/Panasonic_M2), which used two PowerPC 602,<ref name="NGen6"/><ref>[http://www.consoledatabase.com/consoleinfo/3domatsushitam2/ 3DO/Matsushita M2 Console Information]</ref> but it was never marketed.
*[http://www.cpushack.com/CIC/embed/announce/IBMPowerPC602.html Article at the CPUShack]

===PowerPC 603q===
On October 21, 1996, the [fabless semiconductor company](/source/fabless_semiconductor_company) [Quantum Effect Devices](/source/Quantum_Effect_Devices) (QED) announced a PowerPC 603-compatible processor named "'''PowerPC 603q'''" at the [Microprocessor Forum](/source/Microprocessor_Report). Despite its name, it did not have anything in common with any other 603. It was a from the ground up implementation of the 32-bit PowerPC architecture targeted at the high-end embedded market developed over two years. As such, it was small, simple, energy efficient, but powerful; equaling the more expensive 603e while drawing less power. It had an in-order, five-stage pipeline with a single integer unit, a [double-precision](/source/double-precision_floating-point_format) floating-point unit (FPU) and separate 16&nbsp;KB instruction and 8&nbsp;KB data caches. While the integer unit was a brand new design, the FPU was derived from the [R4600](/source/R4600) to save time. It was 69&nbsp;mm<sup>2</sup> small using a 0.5&nbsp;μm fabrication process and drew just 1.2&nbsp;W at 120&nbsp;MHz.<ref>{{cite press release|url=http://infopad.eecs.berkeley.edu/CIC/announce/1996/ppc603q-160.html|title=QED Announces PowerPC Microprocessor Technology Development In Addition To Existing MIPS Microprocessors|publisher=[Quantum Effect Devices](/source/Quantum_Effect_Devices)|date=October 21, 1996|archive-url=https://web.archive.org/web/20070712114611/http://infopad.eecs.berkeley.edu/CIC/announce/1996/ppc603q-160.html|archive-date=July 12, 2007}}</ref><ref>{{cite journal|last1=Turley|first1=Jim|date=November 18, 1996|title=QED's PowerPC 603q Heads for Low Cost|journal=[Microprocessor Report](/source/Microprocessor_Report)|pages=22&ndash;23}}</ref>

The 603q was designed for Motorola, but they withdrew from the contract before the 603q went into full production. As a result, the 603q was canceled as QED could not continue to market the processor since they lacked a PowerPC license of their own.

===PowerPC 613===
'''"PowerPC 613"''' seems to be a name Motorola had given a third generation PowerPC.<ref name="CPUShack-ppc95">[http://www.cpushack.com/CIC/announce/1995/PowerPCRoadMap.html PowerPC revving up for next generation – Speedier RISC ahead through '97]</ref><ref>[https://www.linkedin.com/pub/art-arizpe/1/b0/611 Art Arizpe -Project Manager/Engineering Manager Motorola, 1991–1996]</ref><ref name="MacKiDo-codenames">[http://www.mackido.com/CodeNames/Processors.html Processor Codenames – PowerPC's]</ref> It supposedly was renamed "[PowerPC 750](/source/PowerPC_750)" in response to [Exponential Technology](/source/Exponential_Technology)'s [x704](/source/x704) processor, which was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

===PowerPC 614===
Similar to PowerPC 613, the '''"PowerPC 614"''' might have been a name given by Motorola to a third generation PowerPC,<ref name="CPUShack-ppc95" /><ref name="MacKiDo-codenames"/> and later renamed by the same reason as 613. It has been suggested that the part was renamed "[PowerPC 7400](/source/PowerPC_G4)", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

===PowerPC 615===
The "'''PowerPC 615'''" is a PowerPC processor announced by IBM in 1994, but that never reached [mass production](/source/mass_production). Its main feature was to incorporate an [x86](/source/x86) core on die, thus making the processor able to natively process both PowerPC and x86 instructions.<ref>{{cite web|url=http://www.byte.com/art/9511/sec7/art15.htm|title=Alternate Views of the 615|first1=Tom R.|last1=Halfhill|publisher=[Byte](/source/Byte_(magazine))|archive-url=https://web.archive.org/web/19961220093114/http://www.byte.com/art/9511/sec7/art15.htm|archive-date=December 20, 1996}}</ref> An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 were [Minix](/source/Minix) and a special development version of [OS/2](/source/OS%2F2).<ref>{{cite web|url=https://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/|title=Microsoft killed the PowerPC 615|publisher=[The Register](/source/The_Register)|date=October 1, 1998}}</ref>

It was 330&nbsp;mm<sup>2</sup> large and manufactured by IBM on a 0.35&nbsp;μm process. It was pin compatible with [Intel](/source/Intel)'s [Pentium](/source/Pentium) processors and comparable in speed. The processor was introduced only as a prototype and the program was killed in part by the fact that [Microsoft](/source/Microsoft) never supported the processor. Engineers working on the PowerPC 615 would later find their way to [Transmeta](/source/Transmeta), where they worked on the [Crusoe](/source/Transmeta_Crusoe) processor. With progress having been demonstrated in the development of dynamic translation software, such as Digital's [FX!32](/source/FX!32) technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.<ref name="electronicnews19951106_digital">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1995-11-06_41_2090/mode/1up | title=DEC Unveils FX!32 Tech | magazine=Electronic News | date=6 November 1995 | access-date=12 October 2022 | pages=1,94 }}</ref>{{rp|pages=94|quote="The performance levels the 615 is targeting, as we understand, are so degraded by the fact that you're giving up hardware to put that x86 emulation on-chip that it's just uncompelling."}}

===PowerPC 625===
'''"PowerPC 625"''' was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "[RS64](/source/RS64)". The designation "PowerPC 625" was never used for the final processors.

===PowerPC 630===
'''"PowerPC 630"''' was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the [POWER](/source/IBM_POWER_Instruction_Set_Architecture) and [PowerPC](/source/PowerPC) instruction sets. It was later renamed "[POWER3](/source/POWER3)", probably to distinguish it from the more consumer oriented "PowerPC" processors used by [Apple](/source/Apple_Inc.).

===PowerPC 641===
'''"PowerPC 641"''', codename ''Habanero'', is a defunct PowerPC project by IBM in the 1994–96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor.<ref>{{cite web|url=http://zmoore.net/CRM%20Resume%20070904.pdf|title=Charles Moore's resume|archive-url=https://web.archive.org/web/20110724141432/http://zmoore.net/CRM%20Resume%20070904.pdf|archive-date=July 24, 2011}}</ref><ref>{{cite web|url=http://www.mackido.com/Hardware/G3.html|title=G3's - they just keep getting better|first1=David K.|last1=Every|year=1999|archive-url=https://web.archive.org/web/19991010022633/http://www.mackido.com/Hardware/G3.html|archive-date=October 10, 1999}}</ref>

==See also==
*[PowerPC 970](/source/PowerPC_970)
*[IBM POWER architecture](/source/IBM_POWER_architecture)
*[IBM Power microprocessors](/source/IBM_Power_microprocessors)
*[Power ISA](/source/Power_ISA)
* [List of Mac models grouped by CPU type](/source/List_of_Mac_models_grouped_by_CPU_type)

==References==
{{reflist}}

==Further reading==
*{{cite book |last1=Weiss |first1=Shlomo |last2=Smith |first2=James Edward |title=POWER and PowerPC |date=1994 |publisher=Morgan Kaufmann |isbn=1558602798}} {{mdash}} Relevant parts: Chapter 8 (describes the PowerPC 601), and Chapter 11 (a comparison of the PowerPC 601 and Alpha 21064)

==External links==
*[https://www.mackido.com/Hardware/G2.html PPC 600 at mackido.com]

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Category:Superscalar microprocessors
Category:32-bit microprocessors

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Adapted from the Wikipedia article [PowerPC 600](https://en.wikipedia.org/wiki/PowerPC_600) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/PowerPC_600?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.