# Page attribute table

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The **page attribute table** (**PAT**) is a [processor supplementary capability](/source/Processor_supplementary_capability) extension to the [page table](/source/Page_table) format of certain [x86](/source/X86) and [x86-64](/source/X86-64) microprocessors. Like [memory type range registers](/source/Memory_type_range_registers) (MTRRs), they allow for fine-grained control over how areas of memory are [cached](/source/CPU_cache), and are a companion feature to the MTRRs.[1]

Unlike MTRRs, which provide the ability to manipulate the behavior of caching for a limited number of fixed physical address ranges, Page Attribute Tables allow for such behavior to be specified on a [per-page](/source/Page_(computer_science)) basis, greatly increasing the ability of the [operating system](/source/Operating_system) to select the most efficient behavior for any given task.[2]

## Processors

The PAT is available on [Pentium III](/source/Pentium_III) and newer CPUs, and on non-Intel CPUs.

## See also

- [Write-combining](/source/Write-combining)

## References

1. **[^](#cite_ref-1)** ["Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1"](http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf) (PDF). Intel. Retrieved 2017-05-30.

1. **[^](#cite_ref-2)** ["PAT (Page Attribute Table) in Linux kernel docs"](https://web.archive.org/web/20210121115331/https://www.kernel.org/doc/html/latest/x86/pat.html). Archived from [the original](https://www.kernel.org/doc/html/latest/x86/pat.html) on 2021-01-21. Retrieved 2020-06-02.

## External links

- [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1](http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf) see chapter 11, section 12.

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