# PL-4

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{{about|PL-4, a networking protocol|the PRC missile PL-4|PL-4 (missile)}}

'''PL-4''' or POS-PHY Level 4 was the name of the interface that the interface [SPI-4.2](/source/SPI-4.2) is based on. It was proposed by [PMC-Sierra](/source/PMC-Sierra) to the [Optical Internetworking Forum](/source/Optical_Internetworking_Forum). The name means Packet Over SONET Physical layer level 4. PL-4 was developed by PMC-Sierra in conjunction with the Saturn Development Group.

==Context==
There are two broad categories of chip-to-chip interfaces. The first, exemplified by [PCI-Express](/source/PCI-Express) and [HyperTransport](/source/HyperTransport), supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the [IEEE 802.3](/source/IEEE_802.3) family of [Media Independent Interface](/source/Media_Independent_Interface)s and the Optical Internetworking Forum family of [System Packet Interface](/source/System_Packet_Interface)s. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used between devices in the [Packet over SONET](/source/Packet_over_SONET) and [Optical Transport Network](/source/Optical_Transport_Network), which are the principal protocols used to carry the internet between cities.

==Applications==
PL-4 was designed to be used in systems that support [OC-192](/source/OC-192) [SONET](/source/SONET) interfaces and is sometimes used in [10 Gigabit Ethernet](/source/10_Gigabit_Ethernet) based systems. A typical application of PL-4 (SPI-4.2) is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace.

==Technical details==
The interface consists of (per direction):
* sixteen LVDS pairs for the data path
* one LVDS pair for control
* one LVDS pair for clock at half of the data rate
* two FIFO status lines running at 1/8 of the data rate
* one status clock

The clocking is [Source-synchronous](/source/Source-synchronous) and operates around 700 MHz. Implementations of SPI-4.2 (PL-4) have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets.

==Trivia==
The name is an [acronym](/source/acronym) of an acronym of an acronym as the P in PL stands for POS-PHY and the S in POS-PHY stands for SONET ([Synchronous Optical Network](/source/Synchronous_Optical_Network)).

==History==
PL-4 is a descendant of PL-3 which itself is a descendant of the [ATM Forum](/source/ATM_Forum) UTOPIA family of standards. The UTOPIA standards were developed by the [SATURN Development Group](/source/SATURN_Development_Group) for use in ATM systems.

==See also==
* [PL-3](/source/PL-3)

==External links==
* [https://web.archive.org/web/20051025083456/http://www.oiforum.com/public/impagreements.html OIF Interoperability Agreements]

Category:Network protocols

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Adapted from the Wikipedia article [PL-4](https://en.wikipedia.org/wiki/PL-4) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/PL-4?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.