# Open Verification Library

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**Open Verification Library** (OVL) is a library of property checkers for digital circuit descriptions written in popular [Hardware Description Languages (HDLs)](/source/Hardware_description_language). OVL is currently maintained by [Accellera](/source/Accellera).

## Applications

OVL works by placing modules or components checking specific properties of the circuit alongside regular modules or components. Those special modules are called **checkers** and are tied to circuit signals via **ports**. Some aspects of the checker functionality can be modified by adjusting checker **parameters**. Typical properties verified by OVL checkers include:

- condition that should be always met,

- sequence of conditions that should be met,

- condition that should never occur,

- proper data value (even, odd, within a range, etc.),

- proper value change (e.g. increment or decrement within specified range),

- proper data encoding (e.g. *one hot* or *one cold*),

- proper timing of event (within given number of clock cycles or within window created by trigger events),

- valid protocol of data transmission,

- valid behavior of popular building blocks (e.g. [FIFOs](/source/FIFO_(computing_and_electronics))).

Depending on the selected parameters, OVL checkers can work as assertion, assumption or coverage point checkers. Main source of OVL popularity is the fact that it allows introducing high-level verification concepts to the existing or new designs without requiring new language, e.g. a designer having access to Verilog tools does not need a new language to start using property checking with OVL.

## Supported Languages

While first versions of OVL supported [Verilog](/source/Verilog) and [VHDL](/source/VHDL), most recent versions support (in alphabetical order):

- [PSL](/source/Property_Specification_Language) - Verilog flavour

- [SystemVerilog](/source/SystemVerilog)

- [Verilog](/source/Verilog)

- [VHDL](/source/VHDL)

Depending on the demand, support for two more languages may be added: *[PSL](/source/Property_Specification_Language) - VHDL* flavour and *[SystemC](/source/SystemC)*.

## External links

- OVL section of the Accellera page [\[1\]](http://www.accellera.org/activities/ovl/)

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Adapted from the Wikipedia article [Open Verification Library](https://en.wikipedia.org/wiki/Open_Verification_Library) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Open_Verification_Library?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.