# OpenPIC and MPIC

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In order to compete with [Intel](/source/Intel)'s [Advanced Programmable Interrupt Controller](/source/Advanced_Programmable_Interrupt_Controller) (APIC), which had enabled the first [Intel 486](/source/Intel_486)-based [multiprocessor](/source/Multiprocessor) systems, in early 1995 [AMD](/source/AMD) and [Cyrix](/source/Cyrix) proposed as somewhat similar-in-purpose **OpenPIC** architecture supporting up to 32 processors.[1][2] The OpenPIC architecture had at least declarative support from [IBM](/source/IBM) and [Compaq](/source/Compaq) around 1995.[3] No x86 motherboard was released with OpenPIC however.[4] After the OpenPIC's failure in the x86 market, AMD licensed the [Intel APIC Architecture](/source/Intel_APIC_Architecture) for its [AMD Athlon](/source/AMD_Athlon) and later processors.

IBM however developed their **Multiprocessor Interrupt Controller** (**MPIC**) based on the OpenPIC register specification.[5] In the reference IBM design, the processors share the MPIC over a [DCR bus](/source/CoreConnect#Device_Control_Register_(DCR)_bus), with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.[5] Through various implementations, the MPIC was included in [PowerPC](/source/PowerPC) reference designs and some retail computers.

IBM used a MPIC based on OpenPIC 1.0 in their [RS/6000](/source/RS%2F6000) F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual [8259](/source/8259) on their PCI-ISA bridges.[6] An IBM MPIC was also used in the RS/6000 7046 Model B50.[7]

The [Apple](/source/Apple_Inc.) Hydra [Mac I/O](https://en.wikipedia.org/w/index.php?title=Mac_I/O&action=edit&redlink=1) (MIO) chip (from the 1990s [classic Mac OS](/source/Classic_Mac_OS) era) implemented a MPIC alongside a [SCSI](/source/SCSI) controller, [ADB](/source/Apple_Desktop_Bus) controller, [GeoPort](/source/GeoPort) controller, and timers.[8] The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the [Common Hardware Reference Platform](/source/Common_Hardware_Reference_Platform) was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources.[9] A MPIC was also incorporated in the newer K2 I/O controller used in the [Power Mac G5s](/source/Power_Mac_G5).[10][11]

[Freescale](/source/Freescale) also uses a MPIC ("compatible with the Open PIC") on all its [PowerQUICC](/source/PowerQUICC) and [QorIQ](/source/QorIQ) processors.[12] The Linux [Kernel-based Virtual Machine](/source/Kernel-based_Virtual_Machine) (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants.[13]

## See also

- [Programmable Interrupt Controller](/source/Programmable_Interrupt_Controller) (PIC)

## References

1. **[^](#cite_ref-1)** ["OpenPIC Definition from PC Magazine Encyclopedia"](https://web.archive.org/web/20110606090154/http://www.pcmag.com/encyclopedia_term/0%2C2542%2Ct%3DOpenPIC%26i%3D48497%2C00.asp). Pcmag.com. 1994-12-01. Archived from [the original](https://www.pcmag.com/encyclopedia_term/0%2C2542%2Ct%3DOpenPIC%26i%3D48497%2C00.asp) on 2011-06-06. Retrieved 2011-11-03.

1. **[^](#cite_ref-2)** AMD and Cyrix, [The Open Programmable Interrupt Controller (PIC) Register Interface Specification Revision 1.2](https://web.archive.org/web/20180817035617/http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf), publication no. 19725C, October 1995. Archived from the [original](http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf) on 17 Aug 2018.

1. **[^](#cite_ref-Inc.1995_3-0)** Brooke Crothers (20 March 1995). [*AMD, Cyrix offer up alternative SMP spec*](https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8). [InfoWorld](/source/InfoWorld). p. 8. [ISSN](/source/ISSN_(identifier)) [0199-6649](https://search.worldcat.org/issn/0199-6649).

1. **[^](#cite_ref-4)** André D. Balsa, [Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"](http://linuxgazette.net/issue24/Article3e-7.html) appearing in Issue 24 of Linux Gazette, January 1998

1. ^ [***a***](#cite_ref-mpic_db_5-0) [***b***](#cite_ref-mpic_db_5-1) IBM [Multiprocessor Interrupt Controller. Data Book](https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf) [Archived](https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf) 2014-02-23 at the [Wayback Machine](/source/Wayback_Machine)

1. **[^](#cite_ref-6)** Arca Systems TTAP Evaluation Facility, "[The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security](http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf)", p. 29

1. **[^](#cite_ref-7)** RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107

1. **[^](#cite_ref-8)** [Yellowknife Reference Platform Hardware Design Manual](http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf) [Archived](https://web.archive.org/web/20140221203915/http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf) 2014-02-21 at the [Wayback Machine](/source/Wayback_Machine), p. 11

1. **[^](#cite_ref-9)** Macintosh Technology in the Common Hardware Reference Platform, section "2.4.7 Open PIC Interrupt Controller", p. 11, [ISBN](/source/ISBN_(identifier)) [155860393X](https://en.wikipedia.org/wiki/Special:BookSources/155860393X)

1. **[^](#cite_ref-10)** [Take a Look Inside the G5-Based Dual-Processor Power Mac](http://www.informit.com/articles/article.aspx?p=606582)

1. **[^](#cite_ref-11)** [Power Mac G5 Developer Note (Legacy)](https://web.archive.org/web/20140222145839/https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf), p. 26

1. **[^](#cite_ref-12)** [Freescale MPIC Interrupt Controller Node](https://www.kernel.org/doc/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt)

1. **[^](#cite_ref-13)** ["linux/Documentation/virtual/kvm/devices/mpic.txt at master"](https://github.com/torvalds/linux/blob/master/Documentation/virtual/kvm/devices/mpic.txt). Github.com. 2013-04-30. Retrieved 2014-02-12.

## External links

- [AppleMPIC open source code](http://opensource.apple.com/source/AppleMPIC/) [Archived](https://web.archive.org/web/20130507213727/http://opensource.apple.com/source/AppleMPIC/) 2013-05-07 at the [Wayback Machine](/source/Wayback_Machine)

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Adapted from the Wikipedia article [OpenPIC and MPIC](https://en.wikipedia.org/wiki/OpenPIC_and_MPIC) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/OpenPIC_and_MPIC?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.