# Opcode

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Part of a machine instruction

Machine code General concepts Instruction set Opcode Illegal opcode Opcode table Opcode prefix Operand Addressing mode Instructions NOP Branch Indirect branch Repeat instruction Execute instruction Bit manipulation instructions v t e

In [computing](/source/Computing), an **opcode** (abbreviated from **operation code**)[1][2] is an [enumerated value](/source/Enumeration) that specifies the operation to be performed. Opcodes are employed in hardware devices such as [arithmetic logic units](/source/Arithmetic_logic_unit) (ALUs), [central processing units](/source/Central_processing_units) (CPUs), and software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus. In contrast, in CPUs, the opcode is the portion of a [machine language](/source/Machine_code) [instruction](/source/Instruction_(computer_science)) that specifies the operation to be performed.

## CPUs

Opcodes are found in the machine language instructions of CPUs as well as in some [abstract computing machines](/source/Virtual_machine#Process_virtual_machines). In CPUs, an opcode may be referred to as an **instruction machine code**,[3] **instruction code**,[4] **instruction syllable**,[5][6][7][8] **instruction parcel,** or **opstring**.[9][2] For any particular processor (which may be a general CPU or a more specialized processing unit), the opcodes are defined by the processor's [instruction set architecture](/source/Instruction_set_architecture) (ISA).[10] They can be described using an [opcode table](/source/Opcode_table). The types of operations may include [arithmetic](/source/Arithmetic), data copying, [logical operations](/source/Logical_operation), program control, and special instructions (e.g., [CPUID](/source/CPUID)).[10]

In addition to the opcode, many instructions specify the data (known as [operands](/source/Operand)) the operation will act upon, although some instructions may have implicit operands or none.[10] Some instruction sets have nearly uniform fields for opcode and operand specifiers, whereas others (e.g., [x86](/source/X86) architecture) have a less uniform, variable-length structure.[10][11] Instruction sets can be extended through [opcode prefixes](/source/Opcode_prefix), which add a subset of new instructions made up of existing opcodes following reserved byte sequences.[12]

### Sample opcode table

This table shows opcodes of a simple 8-bit microprocessor, the [Intel 8008](/source/Intel_8008) from 1972.

Each opcode is 8 [bits](/source/Bit) long. Each is shown as a [binary](/source/Binary_number) pattern of ones and zeros in the **Opcode** column. Up to two additional fields may be embedded into the opcode. Some 3-bit fields are labeled DDD, SSS, CC, and ALU. The SSS (source) and DDD (destination) fields specify one of the eight possible 8008 [registers](/source/Processor_register) or memory: A, B, C, D, E, H, L, or M. CC specifies one of eight result conditions that will activate certain JMP, CAL, and RET instructions. ALU specifies one of a possible eight [arithmetic logic unit](/source/Arithmetic_logic_unit) functions to be performed during an instruction, specifically, add, add with carry, subtract, subtract with borrow, logical AND, logical XOR, logical OR, and compare. The **X** in some fields means that either a 1 or 0 can be inserted with [no effect](/source/Don't-care_term).

The fixed ones and zeros are combined with the parameter fields to build the 8-bit opcode. Additionally, the full instruction might require one or two additional bytes of [operands](/source/Operand#Computer_science). These are shown in the second major column of the table, labeled **Operands**. If no operands are required, the column is filled with a dash (—).

Since the ones and zeros are difficult to remember, the **Mnemonic** column shows a short, easy to remember letter code that an [assembly language](/source/Assembly_language) programmer may use to invoke the required opcode.

The **Description** column shows the function performed by the microprocessor when it encounters a specific opcode.

Opcode Operands Mnemonic Description 7 6 5 4 3 2 1 0 b2 b3 0 0 0 0 0 0 0 X — — HLT Halt 0 0 DDD 0 0 0 — — INr DDD ← DDD + 1 (except A and M) 0 0 DDD 0 0 1 — — DCr DDD ← DDD - 1 (except A and M) 0 0 0 0 0 0 1 0 — — RLC A1-7 ← A0-6; A0 ← Cy ← A7 0 0 CC 0 1 1 — — Rcc (RET conditional) If cc true, P ← (stack) 0 0 ALU 1 0 0 data — ADI ACI SUI SBI NDI XRI ORI CPI data A ← A [ALU operation] data 0 0 N 1 0 1 — — RST n (stack) ← P, P ← N x 8 0 0 DDD 1 1 0 data — LrI data (Load r with immediate data) DDD ← data 0 0 X X X 1 1 1 — — RET P ← (stack) 0 0 0 0 1 0 1 0 — — RRC A0-6 ← A1-7; A7 ← Cy ← A0 0 0 0 1 0 0 1 0 — — RAL A1-7 ← A0-6; Cy ← A7; A0 ← Cy 0 0 0 1 1 0 1 0 — — RAR A0-6 ← A1-7; Cy ← A0; A7 ← Cy 0 1 CC 0 0 0 addlo addhi Jcc add (JMP conditional) If cc true, P ← add 0 1 0 0 port 1 — — INP port A ← Port (ports 0-7 only) 0 1 port 1 — — OUT port Port ← A (ports 8-31 only) 0 1 CC 0 1 0 addlo addhi Ccc add (CAL conditional) If cc true, (stack) ← P, P ← add 0 1 X X X 1 0 0 addlo addhi JMP add P ← add 0 1 X X X 1 1 0 addlo addhi CAL add (stack) ← P, P ← add 1 0 ALU SSS — — ADr ACr SUr SBr NDr XRr ORr CPr A ← A [ALU operation] SSS 1 1 DDD SSS — — Lds (Load d with s) DDD ← SSS 1 1 1 1 1 1 1 1 — — HLT Halt 7 6 5 4 3 2 1 0 b2 b3 Mnemonic Description SSS DDD 2 1 0 CC ALU A 0 0 0 FC, C false ADr ADI (A ← A + arg) B 0 0 1 FZ, Z false ACr ACI (A ← A + arg + Cy) C 0 1 0 FS, S false SUr SUI (A ← A - arg) D 0 1 1 FP, P odd SBr SBI (A ← A - arg - Cy) E 1 0 0 TC, C true NDr NDI (A ← A ∧ arg) H 1 0 1 TZ, Z true XRr XRI (A ← A ⊻ arg) L 1 1 0 TS, S true ORr ORI (A ← A ∨ arg) M 1 1 1 TP, P even CPr CPI (A - arg) SSS DDD 2 1 0 CC ALU

## Software instruction sets

Opcodes can be found in [bytecodes](/source/Bytecode) and other representations intended for execution by software interpreters. These often employ slightly higher-level data types and operations than those found in hardware opcodes but are nevertheless constructed along similar lines. Examples include the byte code found in [Java class files](/source/Java_class_file), which are interpreted by [Java virtual machines](/source/Java_virtual_machine), the byte code used in [GNU Emacs](/source/GNU_Emacs) for compiled [Lisp](/source/Lisp_(programming_language)) code, and NET [Common Intermediate Language](/source/Common_Intermediate_Language).[13]

## See also

- [Computer programming portal](https://en.wikipedia.org/wiki/Portal:Computer_programming)

- [Gadget (machine instruction sequence)](/source/Gadget_(machine_instruction_sequence))

- [Illegal opcode](/source/Illegal_opcode)

- [Syllable (computing)](/source/Syllable_(computing))

- [Fused operation](/source/Fused_operation)

## References

1. **[^](#cite_ref-Barron_1978_Opcode_1-0)** [Barron, David William](/source/David_W._Barron) (1978) [1971, 1969]. "2.1. Symbolic instructions". Written at [University of Southampton](/source/University_of_Southampton), Southampton, UK. In Floretin, J. John (ed.). *Assemblers and Loaders*. Computer Monographs (3 ed.). New York, USA: [Elsevier North-Holland Inc.](/source/Elsevier_North-Holland_Inc.) p. 7. [ISBN](/source/ISBN_(identifier)) [0-444-19462-2](https://en.wikipedia.org/wiki/Special:BookSources/0-444-19462-2). [LCCN](/source/LCCN_(identifier)) [78-19961](https://lccn.loc.gov/78-19961). (xii+100 pages)

1. ^ [***a***](#cite_ref-Chiba_2007_2-0) [***b***](#cite_ref-Chiba_2007_2-1) Chiba, Shigeru (2007) [1999]. ["Javassist, a Java-bytecode translator toolkit"](http://www.docjar.org/html/api/javassist/bytecode/InstructionPrinter.java.html). [Archived](https://web.archive.org/web/20200302185725/http://www.docjar.org/html/api/javassist/bytecode/InstructionPrinter.java.html) from the original on 2020-03-02. Retrieved 2016-05-27.

1. **[^](#cite_ref-Intel_1973_MCS-4_3-0)** ["Appendix B - Instruction Machine Codes"](http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf) (PDF). *MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual* (Preliminary ed.). Santa Clara, California, USA: [Intel Corporation](/source/Intel_Corporation). December 1973. pp. B-1 – B-8. MCS-030-1273-1. [Archived](https://web.archive.org/web/20200301235541/http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf) (PDF) from the original on 2020-03-01. Retrieved 2020-03-02.

1. **[^](#cite_ref-Intel_1974_MCS-40_4-0)** Raphael, Howard A., ed. (November 1974). ["The Functions Of A Computer: Instruction Register And Decoder"](http://bitsavers.trailing-edge.com/components/intel/MCS40/MCS-40_Users_Manual_Nov74.pdf) (PDF). *MCS-40 User's Manual For Logic Designers*. Santa Clara, California, USA: [Intel Corporation](/source/Intel_Corporation). p. viii. [Archived](https://web.archive.org/web/20200303024244/http://bitsavers.trailing-edge.com/components/intel/MCS40/MCS-40_Users_Manual_Nov74.pdf) (PDF) from the original on 2020-03-03. Retrieved 2020-03-03. […] Each operation that the processor can perform is identified by a unique binary number known as an instruction code. […]

1. **[^](#cite_ref-Jones_1988_CISC_5-0)** Jones, Douglas W. (June 1988). ["A Minimal CISC"](https://doi.org/10.1145%2F48675.48684). *ACM SIGARCH Computer Architecture News*. **16** (3). New York, USA: [Association for Computing Machinery](/source/Association_for_Computing_Machinery) (ACM): 56–63. [doi](/source/Doi_(identifier)):[10.1145/48675.48684](https://doi.org/10.1145%2F48675.48684). [S2CID](/source/S2CID_(identifier)) [17280173](https://api.semanticscholar.org/CorpusID:17280173).

1. **[^](#cite_ref-Domagała_2012_6-0)** Domagała, Łukasz (2012). ["7.1.4. Benchmark suite"](https://books.google.com/books?id=e6apNOED26kC). [*Application of CLP to instruction modulo scheduling for VLIW processors*](https://books.google.com/books?id=e6apNOED26kC). Gliwice, Poland: Jacek Skalmierski Computer Studio. pp. 80–83 [83]. [ISBN](/source/ISBN_(identifier)) [978-83-62652-42-6](https://en.wikipedia.org/wiki/Special:BookSources/978-83-62652-42-6). [Archived](https://web.archive.org/web/20200302192452/https://books.google.de/books?hl=de&id=e6apNOED26kC&jtp=83) from the original on 2020-03-02. Retrieved 2016-05-28.

1. **[^](#cite_ref-Smotherman_2013_7-0)** Smotherman, Mark (2016) [2013]. ["Multiple Instruction Issue"](https://people.cs.clemson.edu/~mark/330/ilp.txt). School of Computing, Clemson University. [Archived](https://web.archive.org/web/20160528142545/https://people.cs.clemson.edu/~mark/330/ilp.txt) from the original on 2016-05-28. Retrieved 2016-05-28.

1. **[^](#cite_ref-Jones_2016_CISC_8-0)** Jones, Douglas W. (2016) [2012]. ["A Minimal CISC"](http://homepage.cs.uiowa.edu/~jones/arch/cisc/). *Computer Architecture On-Line Collection*. Iowa City, USA: [The University of Iowa](/source/The_University_of_Iowa), Department of Computer Science. [Archived](https://web.archive.org/web/20200302190911/http://homepage.cs.uiowa.edu/~jones/arch/cisc/) from the original on 2020-03-02. Retrieved 2016-05-28.

1. **[^](#cite_ref-Schulman_2005_9-0)** Schulman, Andrew (2005-07-01). ["Finding Binary Clones with Opstrings & Function Digests"](http://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406152). *[Dr. Dobb's Journal](/source/Dr._Dobb's_Journal)*. Part I. Vol. 30, no. 7. [CMP Media LLC](/source/CMP_Media_LLC). pp. 69–73. [ISSN](/source/ISSN_(identifier)) [1044-789X](https://search.worldcat.org/issn/1044-789X). #374. [Archived](https://web.archive.org/web/20200302175401/https://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406152) from the original on 2020-03-02. Retrieved 2020-03-02; Schulman, Andrew (2005-08-01). ["Finding Binary Clones with Opstrings & Function Digests"](http://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406203). *[Dr. Dobb's Journal](/source/Dr._Dobb's_Journal)*. Part II. Vol. 30, no. 8. [CMP Media LLC](/source/CMP_Media_LLC). pp. 56–61. [ISSN](/source/ISSN_(identifier)) [1044-789X](https://search.worldcat.org/issn/1044-789X). #375. [Archived](https://web.archive.org/web/20200302185255/https://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406203) from the original on 2020-03-02. Retrieved 2016-05-28; Schulman, Andrew (2005-09-01). ["Finding Binary Clones with Opstrings & Function Digests"](http://www.drdobbs.com/tools/finding-binary-clones-with-opstrings-fu/184406247). *[CMP Media LLC](/source/CMP_Media_LLC)*. Part III. Vol. 30, no. 9. [United Business Media](/source/United_Business_Media). pp. 64–70. [ISSN](/source/ISSN_(identifier)) [1044-789X](https://search.worldcat.org/issn/1044-789X). #376. [Archived](https://web.archive.org/web/20200302185646/https://www.drdobbs.com/tools/finding-binary-clones-with-opstrings-fu/184406247?pgno=3) from the original on 2020-03-02. Retrieved 2016-05-28.

1. ^ [***a***](#cite_ref-Hennessy_2017_10-0) [***b***](#cite_ref-Hennessy_2017_10-1) [***c***](#cite_ref-Hennessy_2017_10-2) [***d***](#cite_ref-Hennessy_2017_10-3) Hennessy, John L.; Patterson, David A.; [Asanović, Krste](/source/Krste_Asanovi%C4%87); Bakos, Jason D.; Colwell, Robert P.; Bhattacharjee, Abhishek; Conte, Thomas M.; Duato, José; Franklin, Diana; Goldberg, David; Jouppi, Norman P.; Li, Sheng; Muralimanohar, Naveen; Peterson, Gregory D.; Pinkston, Timothy M.; Ranganathan, Parthasarathy; Wood, David A.; Young, Cliff; Zaky, Amr (2017-11-23). *Computer architecture: A quantitative approach* (6 ed.). Cambridge, Massachusetts, USA: [Morgan Kaufmann Publishers](/source/Morgan_Kaufmann_Publishers). [ISBN](/source/ISBN_(identifier)) [978-0-12811905-1](https://en.wikipedia.org/wiki/Special:BookSources/978-0-12811905-1). [OCLC](/source/OCLC_(identifier)) [983459758](https://search.worldcat.org/oclc/983459758).

1. **[^](#cite_ref-Mansfield_1983_11-0)** Mansfield, Richard (1983). ["Introduction: Why Machine Language?"](http://www.atariarchives.org/mlb/introduction.php). [*Machine Language For Beginners*](https://www.atariarchives.org/mlb/index.php). [Compute! Books](/source/Compute!_Books) (1 ed.). Greensboro, North Carolina, USA: [COMPUTE! Publications, Inc.](/source/COMPUTE!_Publications%2C_Inc.), [American Broadcasting Companies, Inc.](/source/American_Broadcasting_Companies%2C_Inc.); [Small System Services, Inc.](/source/Small_System_Services%2C_Inc.) [ISBN](/source/ISBN_(identifier)) [0-942386-11-6](https://en.wikipedia.org/wiki/Special:BookSources/0-942386-11-6). [Archived](https://web.archive.org/web/20080213090055/http://www.atariarchives.org/mlb/introduction.php) from the original on 2008-02-13. Retrieved 2016-05-28.

1. **[^](#cite_ref-12)** Tanenbaum, Andrew S; Austin, Todd (2013). *Structured Computer Organization* (Sixth ed.). Pearson Education, Inc. p. 367. [ISBN](/source/ISBN_(identifier)) [0-13-291652-5](https://en.wikipedia.org/wiki/Special:BookSources/0-13-291652-5).

1. **[^](#cite_ref-bytecode_13-0)** ["bytecode Definition"](https://web.archive.org/web/20121006015213/http://www.pcmag.com/encyclopedia_term/0%2C2542%2Ct%3Dbytecode%26i%3D39108%2C00.asp). *[PC Magazine](/source/PC_Magazine)*. PC Magazine Encyclopedia. Archived from [the original](https://www.pcmag.com/encyclopedia_term/0,2542,t=bytecode&i=39108,00.asp) on 2012-10-06. Retrieved 2015-10-10.

v t e x86 assembly topics Topics Assembly language Comparison of assemblers Disassembler Instruction set Low-level programming language Machine code Microassembler x86 assembly language Assemblers A86/A386 Flat Assembler (FASM) GNU Assembler (GAS) High Level Assembly (HLA) Microsoft Macro Assembler (MASM) Netwide Assembler (NASM) Turbo Assembler (TASM) Open Watcom Assembler (WASM) Programming issues Call stack Flags Carry flag Direction flag Interrupt flag Overflow flag Zero flag Memory address Opcode Program counter Processor register Calling conventions Instruction listings Registers

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Adapted from the Wikipedia article [Opcode](https://en.wikipedia.org/wiki/Opcode) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Opcode?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.