# OR gate > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/OR_gate > Markdown URL: https://mediated.wiki/source/OR_gate.md > Source: https://en.wikipedia.org/wiki/OR_gate > Source revision: 1306143006 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) {{Short description|Digital logic gate type}} {{About|OR in the sense of an electronic logic gate (e.g. CMOS 4071)|OR in the purely logical sense|Logical disjunction}} {{More citations needed|date=September 2012}} The '''OR gate''' is a digital [logic gate](/source/logic_gate) that implements [logical disjunction](/source/logical_disjunction). The OR gate outputs "true" if any of its inputs is "true"; otherwise it outputs "false". The input and output states are normally represented by different [voltage](/source/voltage) levels. ==Description== {| class="wikitable floatright" style="text-align:center" |- ! colspan="3" | OR gate [truth table](/source/truth_table) |- bgcolor="#ddeeff" |colspan=2|'''Input''' || '''Output''' |- bgcolor="#ddeeff" | A || B || A OR B |- |{{no2|0}} || {{no2|0}} || {{no2|0}} |- |{{no2|0}} || {{yes2|1}} || {{yes2|1}} |- |{{yes2|1}} || {{no2|0}} || {{yes2|1}} |- |{{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} Any OR gate can be constructed with two or more inputs. It outputs a 1 if any of these inputs are 1, or outputs a 0 only if all inputs are 0. The inputs and outputs are binary digits ("[bit](/source/bit)s") which have two possible [logical states](/source/truth_value). In addition to 1 and 0, these states may be called true and false, high and low, active and inactive, or other such pairs of symbols. Thus it performs a [logical disjunction](/source/logical_disjunction) (∨) from [mathematical logic](/source/mathematical_logic). The gate can be represented with the plus sign (+) because it can be used for [logical addition](/source/Disjunction_introduction).{{cite web |url=https://www.electronics-tutorials.ws/logic/logic_3.html |website=Electronics Tutorials |title=Logic OR Gate Tutorial|date=20 August 2013 }} Equivalently, an OR gate finds the ''maximum'' between two binary digits, just as the [AND gate](/source/AND_gate) finds the ''minimum''.{{cite web|url=http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/or.html |title=OR Gate |publisher=Hyperphysics.phy-astr.gsu.edu |access-date=2012-09-24}} Together with the [AND gate](/source/AND_gate) and the [NOT gate](/source/NOT_gate), the OR gate is one of three basic logic gates from which any [Boolean circuit](/source/Boolean_circuit) may be constructed. All other [logic gates](/source/logic_gates) may be made from these three gates; any function in binary mathematics may be implemented with them.{{cite book |title=Practical Programmable Circuits: A Guide to PLDs, State Machines, and Microcontrollers |first=James D. |last=Broesch |year=2012 |page=19 |publisher=Elsevier Science |isbn=978-0323139267 |url=https://books.google.com/books?id=I7-v5CBVmfIC&pg=PA20 }} It is sometimes called the '''inclusive OR gate''' to distinguish it from [XOR](/source/XOR_gate), the exclusive OR gate.{{cite report |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |title=Graphical Symbols for Logic Diagrams |id=MIL-STD-806 |date=February 26, 1962 |author=U.S. Department of Defense }} The behavior of OR is the same as XOR except in the case of a 1 for both inputs. In situations where this never arises (for example, in a [full-adder](/source/full-adder)) the two types of gates are interchangeable. This substitution is convenient when a circuit is being implemented using simple [integrated circuit](/source/integrated_circuit) chips which contain only one gate type per chip. ==Symbols== There are two [logic gate symbols](/source/Logic_gate) currently representing the OR gate: the American ([ANSI](/source/American_National_Standards_Institute) or 'military') symbol and the [IEC](/source/International_Electrotechnical_Commission) ('European' or 'rectangular') symbol. The [DIN](/source/DIN) symbol is deprecated.{{cite book|last=Harris|first=David Harris, Sarah|title=Digital design and computer architecture|year=2007|publisher=Morgan Kaufmann|location=San Francisco, Calif.|isbn=9780123704979|pages=21|edition=1st}}{{cite book|last=Brumbach|first=Michael E.|title=Industrial electricity|date=January 2010 |publisher=Delmar|location=Clifton Park, N.Y.|isbn=9781435483743|pages=546|edition=8th}} The "≥1" on the IEC symbol indicates that the output is activated by at least one active input.{{cite report |url=https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf |title=Overview of IEEE Standard 91-1984: Explanation of Logic Symbols |author=Semiconductor Group |publisher=Texas Instruments |id=SDYZ001A |page=4 }}
{{multiple image |align=center |total_width=600 |image1=OR ANSI Labelled.svg |image2=IEC OR.svg |image3=OR DIN.svg |caption1=MIL/ANSI Symbol |caption2=IEC Symbol |caption3=DIN Symbol }}
As of [Unicode](/source/Unicode) 16.0.0, the OR gate is also encoded in the [Symbols for Legacy Computing Supplement](/source/Symbols_for_Legacy_Computing_Supplement) block as {{Unichar|1CC15}}. ==Hardware description and pinout== thumb|right|class=skin-invert-image|upright=0.9|This schematic diagram shows the arrangement of four OR gates within a standard 4071 CMOS integrated circuit. OR gates are basic logic gates, and are available in [TTL](/source/Transistor%E2%80%93transistor_logic) and [CMOS](/source/CMOS) [ICs](/source/integrated_circuit) [logic families](/source/logic_family). The standard 4000 series [CMOS](/source/CMOS) IC is the 4071, which includes four independent two-input OR gates. The TTL device is the 7432. There are many offshoots of the original 7432 OR gate, all having the same pinout but different internal architecture, allowing them to operate in different voltage ranges and/or at higher speeds. In addition to the standard 2-input OR gate, 3- and 4-input OR gates are also available. In the CMOS series, these are: * 4075: triple 3-input OR gate * 4072: dual 4-input OR gate Variations include: * 74LS32: quad 2-input OR gate (low power [Schottky](/source/Schottky_barrier) version) * 74HC32: quad 2-input OR gate (high speed CMOS version) - has lower current consumption/wider voltage range * 74AC32: quad 2-input OR gate (advanced CMOS version) - similar to 74HC32, but with significantly faster switching speeds and stronger drive * 74LVC32: low voltage CMOS version of the same. {{clear}} ==Implementations==
{{multiple image | total_width = 700 | align = center | image1 = CMOS OR.svg | caption1 = [CMOS](/source/CMOS) OR gate (NOT gate is visible on the right) | image2 = NMOS OR gate.png | caption2 = [NMOS](/source/NMOS_logic) OR gate | image3 = Transistor OR Gate.png | caption3 = [BJT](/source/Bipolar_junction_transistor) OR gate | image4 = Diode OR Gate.svg | caption4 = OR gate using [diode](/source/diode)s }}
=== Analytical representation === f(a,b)=a+b-a*b is the analytical representation of OR gate: * f(0,0)=0+0-0*0=0 * f(0,1)=0+1-0*1=1 * f(1,0)=1+0-1*0=1 * f(1,1)=1+1-1*1=1 ===OR gates with many inputs=== OR gates with multiple inputs are designated with the same symbol, with more lines leading in.{{Cite web |url=https://www.allaboutcircuits.com/textbook/digital/chpt-3/multiple-input-gates/ |title=Multiple-input Gates |access-date=2024-02-04 |publisher=All About Circuits}} While direct implementations with more than three inputs are possible in logic families like CMOS, these are inefficient. More efficient implementations use a cascade of [NOR](/source/NOR_gate) and [NAND](/source/NAND_gate) gates, as shown in the picture below. 12-input OR gate via NOR and NAND gates.svg|12-input OR gate realized via a cascade of NOR and NAND gates. ===Alternatives=== {{further|NAND logic|NOR logic}} If no specific OR gates are available, one can be made from NAND or NOR gates in the configuration shown in the image below. Any logic gate can be made from a combination of [NAND](/source/NAND_gate) or [NOR](/source/NOR_gate) gates. {| style="margin:auto; text-align:center;" class="skin-invert-image" |- ! width="250" |Desired gate!!width=150|NAND construction!!width=150|NOR construction |- |Image:OR ANSI Labelled.svg||File:OR from NAND.svg||File:OR from NOR.svg |} ==Wired-OR== thumb|Wired OR gate using open-collector NOR gates With [active low](/source/Logic_level) [open collector](/source/open_collector) logic outputs, as used for control signals in many circuits, an OR function can be produced by wiring together several outputs. This arrangement is called a ''wired OR''. This implementation of an OR function typically is also found in integrated circuits of N or P-type only transistor processes. {{Clear}} ==See also== {{Commons category|OR gates}} *[AND gate](/source/AND_gate) *[NOT gate](/source/Inverter_(logic_gate)) *[NAND gate](/source/NAND_gate) *[NOR gate](/source/NOR_gate) *[XOR gate](/source/XOR_gate) *[XNOR gate](/source/XNOR_gate) *[Boolean algebra](/source/Boolean_algebra) *[Logic gate](/source/Logic_gate) ==References== {{reflist}} {{Logical connectives}} {{DEFAULTSORT:Or Gate}} Category:Logic gates Category:Boolean algebra Category:Digital electronics --- Adapted from the Wikipedia article [OR gate](https://en.wikipedia.org/wiki/OR_gate) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/OR_gate?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.