# Network interface controller

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Hardware component that connects a computer to a network

"Network card" redirects here. For the British Rail discount card, see [Network Railcard](/source/Network_Railcard).

Network interface controller A 1990s Ethernet network interface card that connects to the motherboard via the now-obsolete ISA bus. This combination card features both a BNC connector (left) for use in (now obsolete) 10BASE2 networks and an 8P8C connector (right) for use in 10BASE-T networks. Connects to Motherboard via one of: integrated in chipset or SoC discrete onboard PCI Connector ISA Connector PCIe (including Mini PCIe and M.2) FireWire USB Thunderbolt HDMI (via HDMI Ethernet channel) Network via one of: Ethernet Wi-Fi Fibre Channel ATM FDDI Token Ring ARCNET InfiniBand Speeds Full-duplex or half-duplex: 10 Mbit/s 100 Mbit/s 1 Gbit/s Full-duplex:[1][2] 2.5 Gbit/s 5 Gbit/s 10 Gbit/s up to 160 Gbit/s Common manufacturers Intel Realtek Broadcom (includes former Avago, Emulex) Marvell Technology Group Cavium (formerly QLogic) Mellanox Chelsio

A **network interface controller** (**NIC**, also known as a **network interface card**,[3] **network adapter**, **LAN adapter** and **physical network interface**[4]) is a [computer hardware](/source/Computer_hardware) component that connects a [computer](/source/Computer) to a [computer network](/source/Computer_network).[5]

Early network interface controllers were commonly implemented on [expansion cards](/source/Expansion_card) that plugged into a [computer bus](/source/Computer_bus). The low cost and ubiquity of the [Ethernet](/source/Ethernet) standard means that most newer computers have a network interface controller built into the [motherboard](/source/Motherboard) or contained in a [USB](/source/USB)-connected [dongle](/source/Dongle), although network cards remain available.

Modern network interface controllers offer advanced features such as [interrupt](/source/Interrupt) and [DMA](/source/Direct_memory_access) interfaces to the host processors, support for multiple receive and transmit queues, partitioning into multiple logical interfaces, and on-controller network traffic processing such as the [TCP offload engine](/source/TCP_offload_engine).

## Purpose

The network controller implements the electronic circuitry required to communicate using a specific [physical layer](/source/Physical_layer) and [data link layer](/source/Data_link_layer) standard such as [Ethernet](/source/Ethernet) or [Wi-Fi](/source/Wi-Fi).[a] This provides a base for a full network [protocol stack](/source/Protocol_stack), allowing communication among computers on the same [local area network](/source/Local_area_network) (LAN) and large-scale network communications through routable protocols, such as [Internet Protocol](/source/Internet_Protocol) (IP).

The NIC allows computers to communicate over a computer network, either by using cables or wirelessly. The NIC is both a physical layer and data link layer device, as it provides physical access to a networking medium and, for [IEEE 802](/source/IEEE_802) and similar networks, provides a low-level addressing system through the use of [MAC addresses](/source/MAC_address) that are uniquely assigned to network interfaces.

## Implementation

12 early ISA 8 bit and 16 bit PC network cards. The lower right-most card is an early wireless network card, and the central card with partial beige plastic cover is a PSTN [modem](/source/Modem).

Intel Ophir 82571 dual-port Gigabit Ethernet controller [die](/source/Die_(integrated_circuit))

Network controllers were originally implemented as expansion cards that plugged into a computer bus. The low cost and ubiquity of the Ethernet standard means that most new computers have a network interface controller built into the motherboard, and that method is called LAN on motherboard (LOM). Newer [server](/source/Server_(computing)) motherboards may have multiple network interfaces built in. The Ethernet capabilities are either [integrated](/source/Integrated_circuit) into the motherboard [chipset](/source/Chipset) or implemented via a low-cost dedicated Ethernet chip. A separate network card is typically no longer required unless additional independent network connections are needed or some non-Ethernet type of network is used. A general trend in computer hardware is towards [integrating the various components of systems on a chip](/source/System_on_a_chip), and this is also applied to network interface cards.

An Ethernet network controller typically has an [8P8C](/source/8P8C) socket where the network cable is connected. Older NICs also supplied [BNC](/source/BNC_connector), or [AUI](/source/Attachment_Unit_Interface) connections. Ethernet network controllers typically support 10 [Mbit/s](/source/Megabit_per_second) Ethernet, [100 Mbit/s Ethernet](/source/Fast_Ethernet), and [1000 Mbit/s Ethernet](/source/Gigabit_Ethernet) varieties. Such controllers are designated as *[10/100/1000](/source/10%2F100%2F1000)*, meaning that they can support data rates of 10, 100 or 1000 Mbit/s. [10 Gigabit Ethernet](/source/10_Gigabit_Ethernet) NICs are also available, and, as of November 2014[\[update\]](https://en.wikipedia.org/w/index.php?title=Network_interface_controller&action=edit), are beginning to be available on [computer motherboards](/source/Computer_motherboard).[6][7]

A [Qlogic](/source/Qlogic) QLE3442-CU SFP+ dual-port NIC

Modular designs like [SFP and SFP+](/source/Small_Form-factor_Pluggable) are highly popular, especially for [fiber-optic communication](/source/Fiber-optic_communication). These define a standard receptacle for media-dependent transceivers, so users can easily adapt the network interface to their needs.

[LEDs](/source/LED) adjacent to or integrated into the network connector inform the user of whether the network is connected, and when data activity occurs.

The NIC may include [ROM](/source/ROM) to store its factory-assigned [MAC address](/source/MAC_address).[8]

The NIC may use one or more of the following techniques to indicate the availability of packets to transfer:

- [Polling](/source/Polling_(computer_science)) is where the [CPU](/source/CPU) examines the status of the [peripheral](/source/Peripheral) under program control.

- [Interrupt](/source/Interrupt_request)-driven I/O is where the peripheral alerts the CPU that it is ready to transfer data.

NICs may use one or more of the following techniques to transfer packet data:

- [Programmed input/output](/source/Programmed_input%2Foutput), where the CPU moves the data to or from the NIC to memory.

- [Direct memory access](/source/Direct_memory_access) (DMA), where a device other than the CPU assumes control of the [system bus](/source/System_bus) to move data to or from the NIC to memory. This removes load from the CPU but requires more logic on the card. In addition, a packet buffer on the NIC may not be required, and [latency](/source/Latency_(engineering)) can be reduced.

## Performance and advanced functionality

An [Asynchronous Transfer Mode](/source/Asynchronous_Transfer_Mode) (ATM) network interface

[Intel](/source/Intel) 82574L [Gigabit Ethernet](/source/Gigabit_Ethernet) NIC, a PCI Express ×1 card, which provides two hardware receive queues[9]

**Multiqueue NICs** provide multiple transmit and receive [queues](/source/Queue_(abstract_data_type)), allowing packets received by the NIC to be assigned to one of its receive queues. The NIC may distribute incoming traffic between the receive queues using a [hash function](/source/Hash_function). Each receive queue is assigned to a separate [interrupt](/source/Interrupt); by routing each of those interrupts to different [CPUs](/source/CPU) or [CPU cores](/source/Multi-core_processor), processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed, improving performance.[10][11]

The hardware-based distribution of the interrupts, described above, is referred to as [receive-side scaling](/source/Receive-side_scaling) (RSS).[12]: 82 Purely software implementations also exist, such as the [receive packet steering](/source/Receive_packet_steering) (RPS), [receive flow steering](/source/Receive_flow_steering) (RFS),[10] and [Intel](/source/Intel) *Flow Director*.[12]: 98, 99[13][14][15] Further performance improvements can be achieved by routing the interrupt requests to the CPUs or cores executing the applications that are the ultimate destinations for [network packets](/source/Network_packet) that generated the interrupts. This technique improves [locality of reference](/source/Locality_of_reference) and results in higher overall performance, reduced latency and better hardware utilization because of the higher utilization of [CPU caches](/source/CPU_cache) and fewer required [context switches](/source/Context_switch).

With multi-queue NICs, additional performance improvements can be achieved by distributing outgoing traffic among different transmit queues. By assigning different transmit queues to different CPUs or CPU cores, internal operating system contentions can be avoided. This approach is usually referred to as **transmit packet steering** (XPS).[10]

Some products feature **NIC partitioning** (**NPAR**, also known as **port partitioning**) that uses [SR-IOV](/source/SR-IOV) virtualization to divide a single 10 Gigabit Ethernet NIC into multiple discrete virtual NICs with dedicated bandwidth, which are presented to the firmware and operating system as separate [PCI device functions](/source/PCI_device_function).[3][16]

Some NICs provide a [TCP offload engine](/source/TCP_offload_engine) to offload processing of the entire [TCP/IP](/source/TCP%2FIP) stack to the network controller. It is primarily used with high-speed network interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, for which the processing overhead of the network stack becomes significant.[17]

Some NICs offer integrated [field-programmable gate arrays](/source/Field-programmable_gate_array) (FPGAs) for user-programmable processing of network traffic before it reaches the host computer, allowing for significantly reduced [latencies](/source/Latency_(engineering)) in time-sensitive workloads.[18] Moreover, some NICs offer complete low-latency [TCP/IP stacks](/source/TCP%2FIP_stack) running on integrated FPGAs in combination with [userspace](/source/Userspace) libraries that intercept networking operations usually performed by the [operating system kernel](/source/Operating_system_kernel); Solarflare's open-source **OpenOnload** network stack that runs on [Linux](/source/Linux) is an example. This kind of functionality is usually referred to as **user-level networking**.[19][20][21]

## See also

- [Converged network adapter](/source/Converged_network_adapter) (CNA)

- [Host adapter](/source/Host_adapter)

- [Intel Data Direct I/O](/source/Intel_Data_Direct_I%2FO) (DDIO)

- [Loopback interface](/source/Loopback_interface)

- [Network monitoring interface card](/source/Network_monitoring_interface_card) (NMIC)

- [Virtual network interface](/source/Virtual_network_interface) (VIF)

- [Wireless network interface controller](/source/Wireless_network_interface_controller) (WNIC)

## Notes

1. **[^](#cite_ref-6)** Although other network technologies exist, Ethernet ([IEEE 802.3](/source/IEEE_802.3)) and Wi-Fi ([IEEE 802.11](/source/IEEE_802.11)) have achieved near-ubiquity as LAN technologies since the mid-1990s.

## References

1. **[^](#cite_ref-1)** ["Port speed and duplex mode configuration"](http://docs.ruckuswireless.com/fastiron/08.0.70/fastiron-08070-managementguide/GUID-EDD7D44C-A627-4B76-A9FE-D7657FFF62D3.html). *docs.ruckuswireless.com*. Retrieved 2020-09-25.

1. **[^](#cite_ref-2)** Admin, Arista (2020-04-23). ["Section 11.2: Ethernet Standards - Arista"](https://www.arista.com/en/um-eos/eos-section-11-2-ethernet-standards). *Arista Networks*. Retrieved 2020-09-28.

1. ^ [***a***](#cite_ref-Dell_3-0) [***b***](#cite_ref-Dell_3-1) ["Enhancing Scalability Through Network Interface Card Partitioning"](http://www.dell.com/downloads/global/products/pedge/en/Dell-Broadcom-NPAR-White-Paper.pdf) (PDF). [Dell](/source/Dell). April 2011. Retrieved May 12, 2014.

1. **[^](#cite_ref-4)** ["Physical Network Interface"](https://technet.microsoft.com/en-us/library/dd392944(v=ws.10).aspx). [Microsoft](/source/Microsoft). January 7, 2009.

1. **[^](#cite_ref-networking_01_5-0)** Posey, Brien M. (2006). ["Networking Basics: Part 1 - Networking Hardware"](http://www.windowsnetworking.com/articles_tutorials/networking-basics-part1.html). *Windowsnetworking.com*. TechGenix Ltd. Retrieved 2012-06-09.

1. **[^](#cite_ref-7)** Jim O'Reilly (2014-01-22). ["Will 2014 Be The Year Of 10 Gigabit Ethernet?"](https://web.archive.org/web/20150510043419/http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640). Network Computing. Archived from [the original](http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640) on 2015-05-10. Retrieved 2015-04-29.

1. **[^](#cite_ref-8)** ["Breaking Speed Limits with ASRock X99 WS-E/10G and Intel 10G BASE-T LANs"](http://www.asrock.com/news/index.asp?id=2517). *asrock.com*. 24 November 2014. Retrieved 19 May 2015.

1. **[^](#cite_ref-9)** John Savill (Nov 12, 2000). ["How can I change a network adapter card's MAC address?"](https://www.itprotoday.com/cloud-computing/how-can-i-change-network-adapter-cards-mac-address). Retrieved 2023-11-06.

1. **[^](#cite_ref-10)** ["Intel 82574 Gigabit Ethernet Controller Family Datasheet"](http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf) (PDF). [Intel](/source/Intel). June 2014. p. 1. Retrieved November 16, 2014.

1. ^ [***a***](#cite_ref-linux-net-scaling_11-0) [***b***](#cite_ref-linux-net-scaling_11-1) [***c***](#cite_ref-linux-net-scaling_11-2) Tom Herbert; Willem de Bruijn (May 9, 2014). ["Linux kernel documentation: Documentation/networking/scaling.txt"](https://www.kernel.org/doc/Documentation/networking/scaling.txt). [kernel.org](/source/Kernel.org). Retrieved November 16, 2014.

1. **[^](#cite_ref-12)** ["Intel Ethernet Controller i210 Family Product Brief"](http://www.mouser.com/pdfdocs/i210brief.pdf) (PDF). [Intel](/source/Intel). 2012. Retrieved November 16, 2014.

1. ^ [***a***](#cite_ref-intel-grantley_13-0) [***b***](#cite_ref-intel-grantley_13-1) ["Intel Look Inside: Intel Ethernet"](https://web.archive.org/web/20150326095816/http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf) (PDF). *Xeon E5 v3 (Grantley) Launch*. [Intel](/source/Intel). November 27, 2014. Archived from [the original](http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf) (PDF) on March 26, 2015. Retrieved March 26, 2015.

1. **[^](#cite_ref-14)** ["Linux kernel documentation: Documentation/networking/ixgbe.txt"](https://www.kernel.org/doc/Documentation/networking/ixgbe.txt). [kernel.org](/source/Kernel.org). December 15, 2014. Retrieved March 26, 2015.

1. **[^](#cite_ref-15)** ["Intel Ethernet Flow Director"](http://www.intel.com/content/www/us/en/ethernet-controllers/ethernet-flow-director-video.html). [Intel](/source/Intel). February 16, 2015. Retrieved March 26, 2015.

1. **[^](#cite_ref-16)** ["Introduction to Intel Ethernet Flow Director and Memcached Performance"](http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-ethernet-flow-director.pdf) (PDF). [Intel](/source/Intel). October 14, 2014. Retrieved October 11, 2015.

1. **[^](#cite_ref-17)** Patrick Kutch; Brian Johnson; Greg Rose (September 2011). ["An Introduction to Intel Flexible Port Partitioning Using SR-IOV Technology"](http://www.intel.com/content/dam/www/public/us/en/documents/solution-briefs/10-gbe-ethernet-flexible-port-partitioning-brief.pdf) (PDF). [Intel](/source/Intel). Retrieved September 24, 2015.

1. **[^](#cite_ref-18)** Jonathan Corbet (August 1, 2007). ["Large receive offload"](https://lwn.net/Articles/243949/). [LWN.net](/source/LWN.net). Retrieved May 2, 2015.

1. **[^](#cite_ref-19)** ["High Performance Solutions for Cyber Security"](http://newwavedv.com/markets/defense/cyber-security/). *New Wave Design & Verification*. New Wave DV.

1. **[^](#cite_ref-20)** Timothy Prickett Morgan (2012-02-08). ["Solarflare turns network adapters into servers: When a CPU just isn't fast enough"](https://www.theregister.co.uk/2012/02/08/solarflare_application_onload_engine/). *[The Register](/source/The_Register)*. Retrieved 2014-05-08.

1. **[^](#cite_ref-21)** ["OpenOnload"](http://www.openonload.org/). *openonload.org*. 2013-12-03. Retrieved 2014-05-08.

1. **[^](#cite_ref-22)** Steve Pope; David Riddoch (2008-03-21). ["OpenOnload: A user-level network stack"](https://web.archive.org/web/20140724083136/http://www.openonload.org/openonload-google-talk.pdf) (PDF). *openonload.org*. Archived from [the original](http://www.openonload.org/openonload-google-talk.pdf) (PDF) on 2014-07-24. Retrieved 2014-05-08.

## External links

- ["Physical Network Interface"](https://technet.microsoft.com/en-us/library/dd392944(v=ws.10).aspx). Microsoft.

- ["Predictable Network Interface Names"](http://www.freedesktop.org/wiki/Software/systemd/PredictableNetworkInterfaceNames/). *[Freedesktop.org](/source/Freedesktop.org)*.

- [Multi-queue network interfaces with SMP on Linux](https://greenhost.nl/2013/04/10/multi-queue-network-interfaces-with-smp-on-linux/)

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Adapted from the Wikipedia article [Network interface controller](https://en.wikipedia.org/wiki/Network_interface_controller) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Network_interface_controller?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.